2023 24th International Symposium on Quality Electronic Design (ISQED)最新文献_第5页

Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129283

N. Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu

{"title":"Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators","authors":"N. Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu","doi":"10.1109/ISQED57927.2023.10129283","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129283","url":null,"abstract":"As the demand for data analysis increases rapidly, artificial intelligence (AI) models have been developed for various applications. Many deep neural networks are presented with millions or billions of parameters and operations for AI computation. Therefore, many AI accelerators apply pipelined architectures with simple but dense computational elements for numerous operations. However, manufacturing-induced faults cause a challenge to computational robustness or yield degradation on those AI accelerators. In this paper, we propose a fault mitigation methodology based on decomposable systolic arrays. By leveraging the inherent error resilience of AI applications, our data arrangement can reduce the difference between accurate results and faulty results. Additionally, utilizing both our proposed data arrangement and sign compensation can further mitigate the influence of faults in AI accelerators. In the experiments, our proposed fault mitigation methodology can maintain the application accuracy at a certain level, which outperforms state-of-the-art methods. When 0.1% of multiplier-accumulators are faulty in a systolic array, the array with our proposed fault mitigation methodology can have less than 0.5% accuracy loss while executing ResNet-18 for ImageNet classification.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130588020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGA 基于无监督学习的硬件木马自动检测:以FPGA为例

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129335

Shailesh Rajput, Jaya Dofe, Wafi Danesh

引用次数: 0

Embedded Tutorials 嵌入式教程

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/soccon.2009.5397997

引用次数: 0

Efficient Decryption Architecture for Classic McEliece 经典mcelece的高效解密体系结构

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129325

Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang

{"title":"Efficient Decryption Architecture for Classic McEliece","authors":"Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang","doi":"10.1109/ISQED57927.2023.10129325","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129325","url":null,"abstract":"As one of the candidates evaluated in the process of the National Institute of Standards and Technology (NIST) post-quantum cryptography standardization, the Classic McEliece, is being widely studied for its strong security. In existing decryption architectures, the Goppa decoder is logic resource intensive, and the fast Fourier transform (FFT) unit limits its achievable frequency. In this paper, a novel folded Goppa decoder based on enhanced parallel inversionless Berlekamp-Massey (ePiBM) algorithm is proposed for complexity reduction, and a two-dimensional optimization is adopted to eliminate the frequency bottleneck caused by the FFT unit. In addition, for the finite field inversion, which is a commonly used operation in decryption, an even power-based computation scheme is presented to reduce the cost of logic resources. Based on these optimizations, a complete decryption architecture is finally developed and implemented on the Altera Stratix V FPGA. Experimental results show that the proposed decryption processor can reduce up to 37.6% of logic resources and save the Time×Logic by up to 56.9% over the prior art.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132538577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models FPGA路由延迟模型中的平面图不规则性和组态依赖性

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129290

Gabriel Barajas, J. Greene, Fei Li, James Tandon

{"title":"Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models","authors":"Gabriel Barajas, J. Greene, Fei Li, James Tandon","doi":"10.1109/ISQED57927.2023.10129290","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129290","url":null,"abstract":"Accurate delay estimates for a user application implemented in a Field-Programmable Gate Array (FPGA) are essential for a quality FPGA timing flow and to avoid leaving performance on the table. FPGA inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. The delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the FPGA floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial FPGA software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. This enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114878584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Attacks on Continuous Chaos Communication and Remedies for Resource Limited Devices 对连续混沌通信的攻击与资源有限设备的补救

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129355

Rahul Vishwakarma, Ravi Monani, Amin Rezaei, H. Sayadi, Mehrdad Aliasgari, A. Hedayatipour

{"title":"Attacks on Continuous Chaos Communication and Remedies for Resource Limited Devices","authors":"Rahul Vishwakarma, Ravi Monani, Amin Rezaei, H. Sayadi, Mehrdad Aliasgari, A. Hedayatipour","doi":"10.1109/ISQED57927.2023.10129355","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129355","url":null,"abstract":"The Global Wearable market is anticipated to rise at a considerable rate in the next coming years and communication is a fundamental block in any wearable device. In communication, encryption methods are being used with the aid of microcontrollers or software implementations, which are power-consuming and incorporate complex hardware implementation. Internet of Things (IoT) devices are considered as resource-constrained devices that are expected to operate with low computational power and resource utilization criteria. At the same time, recent research has shown that IoT devices are highly vulnerable to emerging security threats, which elevates the need for low-power and small-size hardware-based security countermeasures. Chaotic encryption is a method of data encryption that utilizes chaotic systems and non-linear dynamics to generate secure encryption keys. It aims to provide high-level security by creating encryption keys that are sensitive to initial conditions and difficult to predict, making it challenging for unauthorized parties to intercept and decode encrypted data. Since the discovery of chaotic equations, there have been various encryption applications associated with them. In this paper, we comprehensively analyze the physical and encryption attacks on continuous chaotic systems in resource-constrained devices and their potential remedies. To this aim, we introduce different categories of attacks of chaotic encryption. Our experiments focus on chaotic equations implemented using Chua’s equation and leverages circuit architectures and provide simulations proof of remedies for different attacks. These remedies are provided to block the attackers from stealing users’ information (e.g., a pulse message) with negligible cost to the power and area of the design.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116752279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Neural Network Partitioning for Fast Distributed Inference 快速分布式推理的神经网络分区

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129343

Robert C. Viramontes, A. Davoodi

引用次数: 0

A SPICE-based Framework to Emulate Quantum Circuits with classical LC Resonators 基于spice的经典LC谐振器量子电路仿真框架

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129351

Md. Mazharul Islam, M. S. Hossain, A. Aziz

引用次数: 0

Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP 使用机器学习，布尔分析和ILP解开闩锁

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129346

Dake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, A. Rittenbach, P. Nuzzo, P. Beerel

{"title":"Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP","authors":"Dake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, A. Rittenbach, P. Nuzzo, P. Beerel","doi":"10.1109/ISQED57927.2023.10129346","DOIUrl":"https://doi.org/10.1109/ISQED57927.2023.10129346","url":null,"abstract":"Logic locking has become a promising approach to provide hardware security in the face of a possibly insecure fabrication supply chain. While many techniques have focused on locking combinational logic (CL), an alternative latch-locking approach in which the sequential elements are locked has also gained significant attention. Latch (LAT) locking duplicates a subset of the flip-flops (FF) of a design, retimes these FFs and replaces them with latches, and adds two types of decoy latches to obfuscate the netlist. It then adds control circuitry (CC) such that all latches must be correctly keyed for the circuit to function correctly. This paper presents a two-phase attack on latch-locked circuits that uses a novel combination of deep learning, Boolean analysis, and integer linear programming (ILP). The attack requires access to the reverse-engineered netlist but, unlike SAT attacks, is oracle-less, not needing access to the unlocked circuit or correct input/output pairs. We trained and evaluated the attack using the ISCAS’89 and ITC’99 benchmark circuits. The attack successfully identifies a key that is, on average, 96.9% accurate and fully discloses the correct functionality in 8 of the tested 19 circuits and leads to low function corruptibility (less than 4%) in 3 additional circuits. The attack run-times are manageable.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123072786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration XOR-CiM:二进制神经网络加速的高效sot - mram计算设计

2023 24th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2023-04-05 DOI: 10.1109/ISQED57927.2023.10129322

M. Morsali, Ranyang Zhou, Sepehr Tabrizchi, A. Roohi, Shaahin Angizi

引用次数: 0