2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)最新文献

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An enhanced three-layer clustering approach and security framework for battlefeld surveillance 一种增强的战场监视三层聚类方法和安全框架
Dhanushik R Macharla, Suhas Tejaskanda
{"title":"An enhanced three-layer clustering approach and security framework for battlefeld surveillance","authors":"Dhanushik R Macharla, Suhas Tejaskanda","doi":"10.1109/ICMDCS.2017.8211719","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211719","url":null,"abstract":"Hierarchical based formation is one of the approaches widely used to minimize the energy consumption in which node with higher residual energy routes the data gathered. Several hierarchical works were proposed in the literature with two and three layered architectures. In the work presented in this paper, we propose an enhanced architecture for three layered hierarchical clustering based approach, which is referred to as enhanced three-layer hierarchical clustering approach (EHCA). The EHCA is based on an enhanced feature of the grid node in terms of its mobility. Further, in our proposed EHCA, we introduce distributed clustering technique for lower level head selection and incorporate security mechanism to detect the presence of any malicious node. We show by simulation results that our proposed EHCA reduces the energy consumption significantly and thus improves the lifetime of the network. Also, we highlight the appropriateness of the proposed EHCA for battlefield surveillance applications.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of digital PID controller for voltage mode control of DC-DC converters DC-DC变换器电压模式控制数字PID控制器的设计
Kartik Sharma, D. K. Palwalia
{"title":"Design of digital PID controller for voltage mode control of DC-DC converters","authors":"Kartik Sharma, D. K. Palwalia","doi":"10.1109/ICMDCS.2017.8211715","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211715","url":null,"abstract":"DC/DC converters are massively used for switchmode regulated power supply, renewable energy conversion systems and electrical drives. Conventionally analog methods were popular for control of these converters. This paper elucidates a digital controller using digital filter architecture, which supports fixed-point algorithm. Digital controller application to DC/DC converters has always been considered because of their superiority over analog controller. In digital controller, the control strategy can be altered or reprogrammed without the need of significant hardware changes. The digital controller improves response of DC-DC converter by varying loop-gain, cross-over frequency and phase margin. Closed loop digital control of buck and boost converter is presented and the results are obtained for varying operating conditions and verified using MATLAB/Simulink.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126955758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Electronically controlled water flow restrictor to limit the domestic wastage of water 电子控制水流限制器,限制家庭用水浪费
Ankith Anisha, R. Menon, Archana Prabhakar
{"title":"Electronically controlled water flow restrictor to limit the domestic wastage of water","authors":"Ankith Anisha, R. Menon, Archana Prabhakar","doi":"10.1109/ICMDCS.2017.8211591","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211591","url":null,"abstract":"Water scarcity affects more than 4 billion people in the world. One of the most critical challenges faced by the world is water shortage. The proposed idea aims to conserve water, by introducing a regulatory system that reduces the rate at which water is obtained at the outlets in a house after a specific volume. The proposed system must be installed at the inlet of every house. Once 80 percent of a specific maximum volume of water is reached, the rate of water flow at all the outlets of house will automatically decrease. The volume of water used is detected by a water flow sensor. A micro-controller receives the input data and electronically reduces the outlet rate of water flow by using a solenoid electro-valve. If this system is implemented in every household, the global scarcity of water can be effectively reduced.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115354835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A SAD architecture for variable block size motion estimation in H.264 video coding H.264视频编码中可变块大小运动估计的SAD结构
C. Santosh, C. P. Rajabai, S. Sivanantham
{"title":"A SAD architecture for variable block size motion estimation in H.264 video coding","authors":"C. Santosh, C. P. Rajabai, S. Sivanantham","doi":"10.1109/ICMDCS.2017.8211731","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211731","url":null,"abstract":"In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is a crucial module/block which plays a major role in computing the efficiency of video coding. Because of variable block size in H.264, motion estimation becomes more complex and requires most efficient hardware for implementation in real-time video coding. The hardware implementation of SAD is done using Comparator and Carry skip adder. The comparator is used to implement the absolute difference unit, which is used to calculate the absolute difference values between each pixel of the current frame and the reference frame. Carry skip adder is used to add all the output values of the absolute difference unit. Carry skip adder improves the performance of the arithmetic operation. It does not wait for carrying to propagate which helps in increasing the speed of operation of adding. Comparator and Carry skip adder unit improves the performance of SAD calculation in terms of speed, area, and power. We had also proposed a control unit for H.264 video. This proposed control unit calculates the SAD output values according to block size given as input to control unit.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of reconfigurable tri-band antenna on chip 芯片上可重构三波段天线的设计
Rahul Pandey, S. Pandey
{"title":"Design of reconfigurable tri-band antenna on chip","authors":"Rahul Pandey, S. Pandey","doi":"10.1109/ICMDCS.2017.8211566","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211566","url":null,"abstract":"In the modern telecommunication system, Reconfigurable Antennas which can radiate on more than one pattern at different frequencies are required. There is a requirement for increased functionality of an antenna within a confined volume for today's transmitting and receiving system. Reconfigurable on chip antennas are a solution to these problems. This paper describes the design of a reconfigurable tri-band antenna which radiates for 2.4GHz(ISM Band), 5.2GHZ and 7.5GHz. This tri-band reconfigurable antenna was simulated on high frequency simulation software (HFSS) and the results for return loss and VSWR plot was obtained for three different frequencies. Thus this antenna will lead to reduction in space and the multiple functionality from a single structure.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130147514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of interface trap charge density on reliability issues of transparent gate recessed channel (TGRC) MOSFET 界面陷阱电荷密度对透明栅槽MOSFET可靠性问题的影响
Ajay Kumar, M. M. Tripathi, R. Chaujar
{"title":"Influence of interface trap charge density on reliability issues of transparent gate recessed channel (TGRC) MOSFET","authors":"Ajay Kumar, M. M. Tripathi, R. Chaujar","doi":"10.1109/ICMDCS.2017.8211538","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211538","url":null,"abstract":"This paper examines the reliability issues of In2O5Sn (ITO) gate electrode (Transparent Gate) Recessed Channel (TGRC) MOSFET by considering the influence of interface trap charges polarity and density present at the Si/SiO2 interface. The reliability of TGRC MOSFET is observed in terms of Linearity and distortion FOMs such as gm, gm3, VIP3. IIP3, HD3. IMD3. Results so obtained revealed that the existence of interface trap charges alter the flat band voltage and thus the threshold voltage; thereby modifying the linearity performance of the device. Moreover, it is also observed that as trap charge density increases, performance escalates considerably. It is found that with positive trap density of 3e12 cm−2, VIP3, IIP3 degrades owing to high distortions (gm3). Thus, results signify that TGRC MOSFET is more reliable to negative trap charges at the Si/SiO2 interface as compared to positive trap charges.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130189115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Home automation using web application and speech recognition 使用web应用程序和语音识别的家庭自动化
C. Baby, Nalin Munshi, Ankit Malik, Kunal Dogra, R. Rajesh
{"title":"Home automation using web application and speech recognition","authors":"C. Baby, Nalin Munshi, Ankit Malik, Kunal Dogra, R. Rajesh","doi":"10.1109/ICMDCS.2017.8211543","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211543","url":null,"abstract":"Home automation — controlling the fans, lights and other electrical appliances in a house using Internet of things is widely preferred in recent days. In this paper, we propose a web application using which the fans, lights and other electrical appliances can be controlled over the Internet. The important features of the web application is that any device connected to the local area network of the house can control the devices and other appliances in the house. The web application used to enable home automation also has a security feature that only enables certain users to access the application. Some lights and fans at home are fully automated based on sensor inputs. Lights are automated based on the inputs from a motion detected and the fans are automated based on the temperature. The door lock can be controlled by giving voice commands. The system has a speech recognition module using Natural Language Processing and hence voice commands can be understood and the home can be automated accordingly.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"20 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Polymer optical waveguide for optical-electrical printed circuit board 光电印刷电路板用聚合物光波导
N. Kumar, T. K. Ramesh
{"title":"Polymer optical waveguide for optical-electrical printed circuit board","authors":"N. Kumar, T. K. Ramesh","doi":"10.1109/ICMDCS.2017.8211557","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211557","url":null,"abstract":"The drastic growth in internet services has led to growth in data sharing between the users. This has led to need for powerful and large data centers, where huge number of storage and computing servers are interconnected. According to the reports, annual data center traffic is growing at a very high growth rate of 25%, of which the major contribution is due to the servers within the data centers, i.e. Intra datacenters. The traffic outside the data center is handled by high-speed optical fiber network. However, within the datacenter the data is handled by both optical and electrical interconnects. It is essential that the fully network infrastructure is made optical to cater to the future needs. To fulfill the intra- and inter-system bandwidth requirements of data centers and HPC (high-performance computers). Though the server racks are connected through active optical cables, the server boards are still fully electrical, i.e. the optical-electrical conversion is done at the board edge. This conversion leads to bandwidth limitations at the server board. In this work we proposed to extend the optical reach to the processing unit i.e., microprocessors and memory unit from board edge. This is achieved by designing an OEPCB (Optical-Electrical Printed Circuit Board) using laser direct writing and to define high-speed optical waveguide. In this work, we target to demonstrate an on-board waveguide technology that can support data rate of 10 Gbps/channel. The demonstrator will enable a platform for further improvement in integration that will enable the next generation High-speed connection in Datacenters.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133996120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of optimal soft-programmable logic controller on multicore processor 多核处理器上最优软可编程控制器的设计与实现
P. Vasu, H. Chouhan, N. Naik
{"title":"Design and implementation of optimal soft-programmable logic controller on multicore processor","authors":"P. Vasu, H. Chouhan, N. Naik","doi":"10.1109/ICMDCS.2017.8211691","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211691","url":null,"abstract":"In the present industrial world, Programmable Logic Controllers (PLCs) are playing a vital role. A Programmable Logic Controller is a solid state user programmable control system with functions to control logic, sequencing, timing, arithmetic data manipulation and counting capabilities. As the applications are becoming more and more complex, the single-core PLCs are unable to meet the high speed execution requirements, so there is a need for high performance PLCs. Scan time is one of the important parameter which determines the performance of PLC. This paper presents an Optimal Software PLC (Soft-PLC) developed using python programming language which runs on multicore processor. The key feature of this Soft-PLC is the identification and parallel execution of independent rungs of ladder logic on multiple core. Our Soft-PLC provides high speed execution and low scan time compared to PLCs which run on single core processor.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130444914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Diffused bit generator model for trng application at CMOS 45nm technology 应用于CMOS 45nm技术的trng扩散位发生器模型
Sundararaman Rajagopalan, Sivaraman Rethinam, G. Lakshmi, Police Mounika, Ravulapenta Vani, D. Chandana
{"title":"Diffused bit generator model for trng application at CMOS 45nm technology","authors":"Sundararaman Rajagopalan, Sivaraman Rethinam, G. Lakshmi, Police Mounika, Ravulapenta Vani, D. Chandana","doi":"10.1109/ICMDCS.2017.8211608","DOIUrl":"https://doi.org/10.1109/ICMDCS.2017.8211608","url":null,"abstract":"True Random Number Generator (TRNG) occupies a commendable position in various information security applications. Random numbers are the one which need to possess the properties of uniform distribution and statically independent. Diffused bit Generator (DBG) is a reliable entropy source and core component to produce the sequence of random bits. The bits emanating from DBG is usually further sampled for n-bit random number generation. In this work, an ASIC implementation of a DBG unit constructed with the integration of LFSR (Linear Feedback Shift Register) and CA (Cellular Automata) has been proposed. This model is designed and simulated using cadence virtuoso tool with 45 nm technology. To validate the design, Transient, AC and DC analyses have been performed.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131929488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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