Influence of interface trap charge density on reliability issues of transparent gate recessed channel (TGRC) MOSFET

Ajay Kumar, M. M. Tripathi, R. Chaujar
{"title":"Influence of interface trap charge density on reliability issues of transparent gate recessed channel (TGRC) MOSFET","authors":"Ajay Kumar, M. M. Tripathi, R. Chaujar","doi":"10.1109/ICMDCS.2017.8211538","DOIUrl":null,"url":null,"abstract":"This paper examines the reliability issues of In2O5Sn (ITO) gate electrode (Transparent Gate) Recessed Channel (TGRC) MOSFET by considering the influence of interface trap charges polarity and density present at the Si/SiO2 interface. The reliability of TGRC MOSFET is observed in terms of Linearity and distortion FOMs such as gm, gm3, VIP3. IIP3, HD3. IMD3. Results so obtained revealed that the existence of interface trap charges alter the flat band voltage and thus the threshold voltage; thereby modifying the linearity performance of the device. Moreover, it is also observed that as trap charge density increases, performance escalates considerably. It is found that with positive trap density of 3e12 cm−2, VIP3, IIP3 degrades owing to high distortions (gm3). Thus, results signify that TGRC MOSFET is more reliable to negative trap charges at the Si/SiO2 interface as compared to positive trap charges.","PeriodicalId":314717,"journal":{"name":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMDCS.2017.8211538","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper examines the reliability issues of In2O5Sn (ITO) gate electrode (Transparent Gate) Recessed Channel (TGRC) MOSFET by considering the influence of interface trap charges polarity and density present at the Si/SiO2 interface. The reliability of TGRC MOSFET is observed in terms of Linearity and distortion FOMs such as gm, gm3, VIP3. IIP3, HD3. IMD3. Results so obtained revealed that the existence of interface trap charges alter the flat band voltage and thus the threshold voltage; thereby modifying the linearity performance of the device. Moreover, it is also observed that as trap charge density increases, performance escalates considerably. It is found that with positive trap density of 3e12 cm−2, VIP3, IIP3 degrades owing to high distortions (gm3). Thus, results signify that TGRC MOSFET is more reliable to negative trap charges at the Si/SiO2 interface as compared to positive trap charges.
界面陷阱电荷密度对透明栅槽MOSFET可靠性问题的影响
本文通过考虑Si/SiO2界面上存在的界面陷阱电荷极性和密度的影响,研究了In2O5Sn (ITO)栅电极(透明栅)凹槽沟道(TGRC) MOSFET的可靠性问题。从线性度和畸变度方面考察了TGRC MOSFET的可靠性,如gm、gm3、VIP3。IIP3 HD3。IMD3。结果表明,界面陷阱电荷的存在改变了平带电压,从而改变了阈值电压;从而修改器件的线性性能。此外,还观察到,随着陷阱电荷密度的增加,性能大大提升。研究发现,当陷阱密度为3e12 cm−2时,VIP3和IIP3由于高畸变(gm3)而降解。因此,结果表明,与正电荷相比,TGRC MOSFET在Si/SiO2界面处具有更可靠的负电荷陷阱。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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