2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第3页

Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach 设计自动化任务调度，以增强最先进的布局感知大小方法的并行执行

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0860

David Neves, R. Martins, N. Lourenço, N. Horta

引用次数: 2

Monitoring of MTL specifications with IBM's spiking-neuron model 使用IBM的峰值神经元模型监控MTL规范

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0139

K. Selyunin, Thang Nguyen, E. Bartocci, D. Ničković, R. Grosu

{"title":"Monitoring of MTL specifications with IBM's spiking-neuron model","authors":"K. Selyunin, Thang Nguyen, E. Bartocci, D. Ničković, R. Grosu","doi":"10.3850/9783981537079_0139","DOIUrl":"https://doi.org/10.3850/9783981537079_0139","url":null,"abstract":"This paper shows how to use the IBM's TrueNorth spiking neuron model, for monitoring if a digital signal satisfies a metric temporal-logic (MTL) specification. TrueNorth spiking neurons are universal computation blocks, which can perform a variety of deterministic or stochastic tasks (e.g., Boolean/arithmetic operations, filtering, and convolution) depending on the configuration of their parameters. We show how to set these parameters for the deterministic TrueNorth neural-model in order to recognize MTL operators. A TrueNorth circuit then behaves as a runtime MTL monitor. We demonstrate how to translate the neural monitor to synthesizable HDL-code on Xilinx's Zedboard using high-level synthesis. To the best of our knowledge, this is the first application of the IBM's TrueNorth model for runtime monitoring. It also demonstrates the complete flow from a high-level specification to the implementation of a neural monitor in FPGA. As a byproduct, the paper also introduces the first open-source FPGA implementation of the deterministic TrueNorth model. We demonstrate the usefulness of our approach on a case study, the launching of a missile from a battle ship.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Automated test generation for Debugging arithmetic circuits 用于调试算术电路的自动测试生成

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0823

Farimah Farahmandi, P. Mishra

{"title":"Automated test generation for Debugging arithmetic circuits","authors":"Farimah Farahmandi, P. Mishra","doi":"10.3850/9783981537079_0823","DOIUrl":"https://doi.org/10.3850/9783981537079_0823","url":null,"abstract":"Optimized and custom arithmetic circuits are widely used in embedded systems such as multimedia applications, cryptography systems, signal processing and console games. Debugging of arithmetic circuits is a challenge due to increasing complexity coupled with non-standard implementations. Existing equivalence checking techniques produce a remainder to indicate the presence of a potential bug. However, bug localization remains a major bottleneck. Simulation-based validation using random or constrained-random tests are not effective and can be infeasible for complex arithmetic circuits. In this paper, we present an automated test generation and bug localization technique for debugging arithmetic circuits. This paper makes two important contributions. We propose an automated approach for generating directed tests by suitable assignments of input variables to make the reminder non-zero. The generated tests are guaranteed to activate the unknown bug. We also propose a bug detection and correction technique by utilizing the patterns of remainder terms as well as the intersection of regions activated by the generated tests. Our experimental results demonstrate that the proposed approach can be used for automated debugging of complex arithmetic circuits.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130762959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Automotive V2X on phones: Enabling next-generation mobile ITS apps 手机上的汽车V2X:实现下一代移动ITS应用

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_1025

Jason H. Gao, L. Peh

引用次数: 7

Reliability and performance trade-offs for 3D NoC-enabled multicore chips 支持3D noc的多核芯片的可靠性和性能权衡

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0288

Sourav Das, J. Doppa, P. Pande, K. Chakrabarty

{"title":"Reliability and performance trade-offs for 3D NoC-enabled multicore chips","authors":"Sourav Das, J. Doppa, P. Pande, K. Chakrabarty","doi":"10.3850/9783981537079_0288","DOIUrl":"https://doi.org/10.3850/9783981537079_0288","url":null,"abstract":"Three-dimensional (3D) integration provides the benefits of better performance, lower power consumption, and increased bandwidth through the use of vertical interconnects and 3D stacking. The vertical interconnects enable the design of a high-bandwidth and energy-efficient small-world (SW) network-based 3D network-on-Chip (3D SWNoC) for massive multicore platforms. However, the anticipated performance gain of a 3D SWNoC-enabled multicore chip may be compromised due to the potential failures of through-silicon-vias (TSVs) that are predominantly employed as vertical interconnects. In particular, due to the non-homogeneous traffic patterns, heavily used TSVs may wear-out quickly and can also contribute to the wear-out of neighboring TSVs. As a result, the mean-time-to-failure (MTTF) of those TSVs will decrease, which will adversely affect the overall lifetime of the chip. In this paper, we address this traffic-dependent TSV wear-out problem in 3D SWNoC. We demonstrate that by employing an adaptive routing mechanism, we can improve the MTTF of 3D SWNoC significantly while still providing 21% lower energy-delay-product (EDP) compared to a conventional 3D MESH.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Efficient monitoring of loose-ordering properties for SystemC/TLM 有效监控SystemC/TLM的松散排序属性

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0609

Yuliia Romenska, F. Maraninchi

引用次数: 0

Path selection and sensor insertion flow for age monitoring in FPGAs fpga年龄监测的路径选择和传感器插入流程

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0801

Mohammad Ebrahimi, Zana Ghaderi, E. Bozorgzadeh, Z. Navabi

引用次数: 11

Leverage Emerging Technologies For DPA-Resilient Block Cipher Design 利用新兴技术进行dpa弹性分组密码设计

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0992

Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, François-Xavier Standaert, Yier Jin

{"title":"Leverage Emerging Technologies For DPA-Resilient Block Cipher Design","authors":"Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, François-Xavier Standaert, Yier Jin","doi":"10.3850/9783981537079_0992","DOIUrl":"https://doi.org/10.3850/9783981537079_0992","url":null,"abstract":"Emerging devices have been designed and fabricated to extend Moore's Law. While the benefits over traditional metrics such as power, energy, delay, and area certainly apply to emerging device technologies, new devices may offer additional benefits in addition to improvements in the aforementioned metrics. In this sense, we consider how new transistor technologies could also have a positive impact on hardware security. More specifically, we consider how tunneling FETs (TFET) and silicon nanowire FETs (SiNW FETs) could offer superior protection to integrated circuits and embedded systems that are subject to hardware-level attacks - e.g., differential power analysis (DPA). Experimental results on SiNW FET and TFET CML gates are presented. In addition, simulation results of utilizing TFET CML on a light-weight cryptographic circuit, KATAN32, show that TFET-based current mode logic (CML) can both improve DPA resilience and preserve low power consumption in the target design. Compared to the CMOS-based CML designs, the TFET CML circuit consumes 15 times less power while achieving a similar level of DPA resistance.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124174375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache 具有堆叠L2高速缓存的多核加速器的高能效3-D片上互连

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0205

K. Kang, Sangho Park, Jong-Bae Lee, L. Benini, G. Micheli

引用次数: 2

Topaz: Mining high-level safety properties from logic simulation traces 黄玉:从逻辑模拟轨迹中挖掘高级安全属性

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0529

Ahmed Nassar, F. Kurdahi, S. Zantout

引用次数: 3