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2022 International Conference on IC Design and Technology (ICICDT)最新文献

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Layout-Configurable and Low-Loss Impedance Matching Circuits Built of Slim CMOS Transmission Lines 基于纤细CMOS传输线的可配置布局和低损耗阻抗匹配电路
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933094
Hongyu Bao, Yu-Ting Chu, S. Lam
{"title":"Layout-Configurable and Low-Loss Impedance Matching Circuits Built of Slim CMOS Transmission Lines","authors":"Hongyu Bao, Yu-Ting Chu, S. Lam","doi":"10.1109/ICICDT56182.2022.9933094","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933094","url":null,"abstract":"Using slim on-chip transmission lines of a compact multi-metallization structure, millimeter-wave impedance matching circuits are constructed by two open stubs. In a typical 50-Ω system, an impedance transformation ratio of 1:5 is achieved by configuring multiple transmission line segments of 60.5 Ω, 32.5 Ω and 50 Ω in their characteristic impedance Z0. Based on a 65-nm CMOS process, the design gives an insertion loss of 1.0 dB at 60 GHz, according to 3D electromagnetic simulation. The reflection loss is also fairly low with |S11| ≈ -16 dB. The low-loss impedance transformer has a broad bandwidth of 25.6 GHz for |S11| < -10 dB. The bandwidth is also broad in a simple quarter-wavelength transformer but with about 1.4 dB insertion loss. With its compact structure, the layout of the transmission line segments can be easily configured to fit the floor-planning of a millimeter-wave integrated circuit, occupying a minimal chip area (< 17 μm in width).","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127188312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Slim Transmission Line Design with Patterned Ground Shields for CMOS mm-Wave Integrated Circuits CMOS毫米波集成电路中带图案地屏蔽的纤细传输线设计
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933117
Hongyu Bao, Jichun Shi, S. Lam
{"title":"A Slim Transmission Line Design with Patterned Ground Shields for CMOS mm-Wave Integrated Circuits","authors":"Hongyu Bao, Jichun Shi, S. Lam","doi":"10.1109/ICICDT56182.2022.9933117","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933117","url":null,"abstract":"An optimized multi-metallization transmission line design with a slim profile and layout simplicity is proposed for CMOS millimeter-wave integrated circuits (ICs). In its quasi-rectangular coaxial structure, the bottom ground-shielding plate adopts a parallel-strip pattern. With the ground-shielding strips laid out perpendicular to the signal-carrying core, the capacitance per unit length of the on-chip transmission line is reduced while the electric field leakage to the substrate is kept to minimum. In a 65-nm CMOS process, the design gives a low insertion loss (less than 1.57 dB/mm) and a low reflection loss (less than -20 dB) at 60 GHz, as verified by 3D electromagnetic simulation. Besides, by simply adopting different strip spacing in the patterned ground shields, the characteristic impedance Z0 of the transmission line can be adjusted by the IC layout up to 66 Ω or slightly higher. With its layout-adjustable Z0 and chip-area efficiency (occupying smaller than 17 μm in width), the transmission line design is potentially versatile for constructing millimeter-wave passive circuits such as Wilkinson power dividers/combiners and impedance matching circuits.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116610102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High-Efficient DC-DC Converter Based on Hybrid SI-SC Topology for Portable Devices 基于SI-SC混合拓扑的便携式高效DC-DC变换器
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933120
V. Nguyen, Truong Pham, Thu-Hong Luu, Thuy-Linh Nguyen, Huu-Tho Nguyen, Van‐Phuc Hoang, Xuan Nam Tran, Van-Huan Nguyen, Van-Ha Nguyen
{"title":"High-Efficient DC-DC Converter Based on Hybrid SI-SC Topology for Portable Devices","authors":"V. Nguyen, Truong Pham, Thu-Hong Luu, Thuy-Linh Nguyen, Huu-Tho Nguyen, Van‐Phuc Hoang, Xuan Nam Tran, Van-Huan Nguyen, Van-Ha Nguyen","doi":"10.1109/ICICDT56182.2022.9933120","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933120","url":null,"abstract":"This paper presents a DC-DC converter circuit using a hybrid switched inductor-switched capacitor (SI -SC) topology for Li-Ion battery powered devices. This is a combination structure of 3-level converter and traditional buck converter. Thanks to redistributing the charging of the parasitic capacitor to another flying capacitor in the opposite-phase SC instead of discharging to ground, the power efficiency can be improved. Simulation results indicate that the maximum efficiency can be achieved is 88% which is 17% higher than that of the traditional circuit under the same conditions. The ripple of the output voltage and the current on the inductor are reduced in comparison to those of the traditional circuit. At the output voltage of 1 V, the output voltage ripple gains less than 5% of the output voltage while on-inductor current ripple anticipated less than 7.8% of the average current.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128576540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Invited Talk #24: Integration of InGaAs HEMTs with Si CMOS for energy efficient hybrid circuits: Exploring the path for future wireless communication technologies 邀请演讲#24:InGaAs hemt与Si CMOS的节能混合电路集成:探索未来无线通信技术的道路
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933122
{"title":"Invited Talk #24: Integration of InGaAs HEMTs with Si CMOS for energy efficient hybrid circuits: Exploring the path for future wireless communication technologies","authors":"","doi":"10.1109/icicdt56182.2022.9933122","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933122","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121417802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Invited Talk #2: Enabling Edge-AI with Binarized spiking neural network using STT-MRAMs 特邀演讲#2:使用stt - mram实现带有二值化峰值神经网络的Edge-AI
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933096
{"title":"Invited Talk #2: Enabling Edge-AI with Binarized spiking neural network using STT-MRAMs","authors":"","doi":"10.1109/icicdt56182.2022.9933096","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933096","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124555146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Keynote #3: Computer-aided design of materials and devices in the quantum-technology era 主题演讲#3:量子技术时代材料和器件的计算机辅助设计
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933114
{"title":"Keynote #3: Computer-aided design of materials and devices in the quantum-technology era","authors":"","doi":"10.1109/icicdt56182.2022.9933114","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933114","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134252669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Field-Plate Integrated Mesa-Type InGaAs/InP Avalanche Photodiode 新型场板集成台面型InGaAs/InP雪崩光电二极管
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933080
Xuanqi Chen, Jishen Zhang, Haiwen Xu, Rui Shao, Yuxuan Wang, Gerui Zheng, Xiao Gong
{"title":"Novel Field-Plate Integrated Mesa-Type InGaAs/InP Avalanche Photodiode","authors":"Xuanqi Chen, Jishen Zhang, Haiwen Xu, Rui Shao, Yuxuan Wang, Gerui Zheng, Xiao Gong","doi":"10.1109/ICICDT56182.2022.9933080","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933080","url":null,"abstract":"For the first time, we proposed and investigated a field-plate (FP) integrated mesa-type InGaAs/InP avalanche photodiode (APD). The shallow-mesa structure helps to suppress the surface effect. At the same time, the FP can minimize the electric field crowding at the mesa edges to avoid the pre-mature breakdown, which could be realized via simple fabrication processes. The impact of FP's length, thickness, and material are considered and investigated by the Sentaurus TCAD simulation, where the effectiveness of our structure is confirmed.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134392960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enablement of CMOS integrated sensor, harvesting and storage applications by ferroelectric HfO2 CMOS集成传感器的实现，铁电HfO2的采集和存储应用
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933079
W. Weinreich, M. Lederer, M. Czernohorsky
{"title":"Enablement of CMOS integrated sensor, harvesting and storage applications by ferroelectric HfO2","authors":"W. Weinreich, M. Lederer, M. Czernohorsky","doi":"10.1109/ICICDT56182.2022.9933079","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933079","url":null,"abstract":"The CMOS compatible material hafnium dioxide shows the ferroelectric effect if deposited as thin film and stabilized in the orthorhombic phase. Next to the scaling potential of ferroelectric memories like FRAM or FeFET, the inherent pyroelectric and piezoelectric properties can be addressed. Indeed, both effects are proven in HfO2 thin films and the according coefficients surpass further CMOS compatible materials and partially reach the high values of common non-CMOS materials like PZT. By that, silicon integration of miniaturized sensors, energy harvesters and energy storage is possible and the current status of developing such applications is reviewed in this paper.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125294078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Invited Talk #9: Ferroelectric Capacitive Memory for Storage and In-memory Computing 特邀演讲#9:用于存储和内存计算的铁电电容存储器
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/icicdt56182.2022.9933082
{"title":"Invited Talk #9: Ferroelectric Capacitive Memory for Storage and In-memory Computing","authors":"","doi":"10.1109/icicdt56182.2022.9933082","DOIUrl":"https://doi.org/10.1109/icicdt56182.2022.9933082","url":null,"abstract":"","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Systematic Study on Positive Bias Temperature Instability(PBTI) of ZrO2-based Ge nMOSFETs with Interlayer Passivations 层间钝化zro2基Ge nmosfet正偏置温度不稳定性的系统研究
2022 International Conference on IC Design and Technology (ICICDT) Pub Date : 2022-09-21 DOI: 10.1109/ICICDT56182.2022.9933130
Lulu Chou, Xiao Yu, Huan Liu, Yan Liu, G. Han, Yue Hao
{"title":"Systematic Study on Positive Bias Temperature Instability(PBTI) of ZrO2-based Ge nMOSFETs with Interlayer Passivations","authors":"Lulu Chou, Xiao Yu, Huan Liu, Yan Liu, G. Han, Yue Hao","doi":"10.1109/ICICDT56182.2022.9933130","DOIUrl":"https://doi.org/10.1109/ICICDT56182.2022.9933130","url":null,"abstract":"In this work, the positive bias temperature instability (PBTI) characteristics of ZrO<inf>2</inf>-based Ge n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with different interlayer (IL) passivation were systematically studied. The threshold voltage (V<inf>TH</inf>) shift, maximum transconductance (g<inf>max</inf>), and the trapping behaviors of devices after stress and recovery procedure are characterized. The generation of the interfacial state dominates the PBTI degradation, and the location of trap generation occurs at the Ge/IL interface rather than at the IL/ZrO<inf>2</inf> interface only, resulting in the g<inf>max</inf> degradation along with the VTH shift. The device with Al<inf>2</inf>O<inf>3</inf>/GeO<inf>x</inf> IL exhibits higher performance on mobility, while the SiO<inf>2</inf> IL sample has a higher voltage acceleration exponent(γ), and larger V<inf>OV</inf> for achieving a 10-year lifetime.","PeriodicalId":311289,"journal":{"name":"2022 International Conference on IC Design and Technology (ICICDT)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124811088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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