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2015 International SoC Design Conference (ISOCC)最新文献

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A robust and parallel-friendly distance image based hand detection 一种鲁棒且并行友好的基于距离图像的手部检测方法
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401651
Zhaohua Yi, Xiaoqi Hu, B. Jang, Kyung Ki Kim
{"title":"A robust and parallel-friendly distance image based hand detection","authors":"Zhaohua Yi, Xiaoqi Hu, B. Jang, Kyung Ki Kim","doi":"10.1109/ISOCC.2015.7401651","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401651","url":null,"abstract":"Hand detection plays an important role in Human Computer Interaction (HCI). Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based approaches, however, are easily distorted by noises and other skin color segments. In this paper, we present a distance image based approach using CPU-GPU heterogeneous computing. Our experiments demonstrate that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate where 80.36% of cases have more than 3 fingers detected on commodity processors. We also achieved 5.0 times speed-up for 320×240 images, and 17.5 times for 640×480 images.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115527192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Chopper stabilized analog front-end IC with improved ripple reduction loop 斩波稳定模拟前端IC与改进纹波减少回路
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401731
Yunjong Park, Haryong Song, Hyungsup Kim, H. Ko
{"title":"Chopper stabilized analog front-end IC with improved ripple reduction loop","authors":"Yunjong Park, Haryong Song, Hyungsup Kim, H. Ko","doi":"10.1109/ISOCC.2015.7401731","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401731","url":null,"abstract":"This paper presents a chopper stabilized analog front-end (AFE) IC with enhanced ripple reduction loop for resistive sensor application. The chopper stabilization is effective solution to reduce the low frequency noise, however, suffers from severe output ripple due to the modulated amplifier offset. We proposed a chopper stabilized resistive AFE with improved ripple reduction loop (RRL). The proposed RRL can achieve low noise and low power characteristics while maintaining small circuit area consumption.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115612157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of HOG based pedestrian detector 基于HOG的行人检测器的FPGA实现
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401776
Matthew Jacobsen, Zhaowei Cai, N. Vasconcelos
{"title":"FPGA implementation of HOG based pedestrian detector","authors":"Matthew Jacobsen, Zhaowei Cai, N. Vasconcelos","doi":"10.1109/ISOCC.2015.7401776","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401776","url":null,"abstract":"We present a FPGA implementation of a pedestrian detector that can process VGA video at a frame rate of 30-40 frames per second in real time. The architecture implements an offline trained boosted detector in an attentional cascade. The cascade evaluates each frame using histogram of gradient (HOG) features in the LUV color space. Pedestrian targets are identified at 27 scales. Feature aggregation allows the design to operate on fewer candidate windows that would normally be required for a 640×480 frame. The design is implemented on a Xilinx Zynq FPGA using a FMC for video input. Video frames are buffered in off-chip DRAM and then streamed through a processing pipeline. The pipeline performs color space conversion, frame rescaling, HOG feature extraction, and candidate evaluation in a sliding window. The candidate evaluation is parallelized to evaluate two windows at a time. The entire pipeline is parallelized to evaluate multiple scales per frame.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121913424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A sorting-based micro-bump assignment for 3D ICs 基于排序的3D集成电路微凸分配
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401697
Ran Zhang, Tieyuan Pan, Takahiro Watanabe
{"title":"A sorting-based micro-bump assignment for 3D ICs","authors":"Ran Zhang, Tieyuan Pan, Takahiro Watanabe","doi":"10.1109/ISOCC.2015.7401697","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401697","url":null,"abstract":"Recently RDLs (Re-Distribution Layers) and micro-bumps are widely adopted in 3D IC designs. In this research, a sorting-based micro-bump assignment method is proposed. The approach initially assigns the I/O pads to micro-bumps by sorting the Manhattan distance between them. Then single layer routing in two RDLs are carried out respectively. The experimental results show that the proposed method is able to obtain the routes with shorter total wire length in reasonable CPU times.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124049850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Shared CSD complex constant multiplier for parallel FFT processors 用于并行FFT处理器的共享CSD复常数乘法器
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401648
T. Nguyen, Hanho Lee
{"title":"Shared CSD complex constant multiplier for parallel FFT processors","authors":"T. Nguyen, Hanho Lee","doi":"10.1109/ISOCC.2015.7401648","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401648","url":null,"abstract":"This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix -24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A real-time cascade pedestrian detection based on heterogeneous features 基于异构特征的实时级联行人检测
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401781
Zhaowei Cai, N. Vasconcelos
{"title":"A real-time cascade pedestrian detection based on heterogeneous features","authors":"Zhaowei Cai, N. Vasconcelos","doi":"10.1109/ISOCC.2015.7401781","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401781","url":null,"abstract":"In this paper, we are introducing a real-time pedestrian detector in traffic scenes. To improve the running efficiency of the whole detection system, a cascade framework is implemented. Three heterogeneous types of features are used, including aggregate channel feature (ACF), the responses of self-similarity and checkerboard filters on ACF. Based on the observations that 1) these three types of features take different complexities to compute, and 2) most of the false positives are rejected in the former cascade stages, we propose to divide the cascade into 3 parts, and each type of features is selected in each cascade part according to the feature complexity. The ACF features are computed for the whole image before any cascade stage, and the other two types of features are computed when they are needed at specific stages. This strategy significantly outperforms ACF-only features with only a little loss of speed. Finally, we achieve a pedestrian detector with running speed of 10 frames per second on a 640×480 image.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128234281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Static fault analysis for resilient System-on-Chip design 弹性片上系统设计的静态故障分析
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401684
Seong Mo Lee, Seung Eun Lee
{"title":"Static fault analysis for resilient System-on-Chip design","authors":"Seong Mo Lee, Seung Eun Lee","doi":"10.1109/ISOCC.2015.7401684","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401684","url":null,"abstract":"As a process technology is scaling, a reliability problem that may cause a failure in the functionality of the digital circuit becomes an important issue in System-on-Chip (SoC) design. This importance leads to the studies on fault diagnosis and tolerance. In this paper, we propose a static and analytical technique for fault diagnosis focused on the digital circuit. Gate level fault analysis is completed in accordance with characteristic of logic gates and error propagation, predicting a susceptible part of hardware. Gate level fault diagnosis can be realized by parsing a gate level netlist without simulation, reducing the verification time. Moreover, our proposal provides an abstraction between the user and the target system for fault diagnosis and helps users choose appropriate fault-tolerant technology for the system. The error propagation analysis with an example combinational logic shows the feasibility of our proposal for resilient SoC design.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131944176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 12-bit 40-kS/s VCM-based switching C-C SAR ADC 一个12位40-kS/s基于vcm的开关C-C SAR ADC
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401644
Dongjin Kim, Young-Ouk Kim, G. Ahn
{"title":"A 12-bit 40-kS/s VCM-based switching C-C SAR ADC","authors":"Dongjin Kim, Young-Ouk Kim, G. Ahn","doi":"10.1109/ISOCC.2015.7401644","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401644","url":null,"abstract":"A 12-bit 40-kS/s VCM-based switching C-C successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The proposed SAR ADC exploits VCM-based switching method with a C-C segmented digital-to-analog converter (DAC) to reduce the size of the converter. Capacitive sub-DAC with buffer amplifier using offset cancellation is utilized to enhance the linearity of converter. Majority vote comparison technique is employed to alleviate comparator noise and to achieve high accuracy comparison. The prototype ADC is fabricated in a 0.18 μm CMOS process. The ADC shows maximum SNDR and SFDR of 57.1dB and 57.3dB with a 1.8V supply while consuming 66.7μW. It occupies an active die area of 0.22mm2.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130285478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new in-field bad block detection scheme for NAND flash chips 一种新的NAND闪存芯片现场坏块检测方案
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401657
Dongho Kang, Keewon Cho, Sungho Kang
{"title":"A new in-field bad block detection scheme for NAND flash chips","authors":"Dongho Kang, Keewon Cho, Sungho Kang","doi":"10.1109/ISOCC.2015.7401657","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401657","url":null,"abstract":"A NAND flash system has been adopted as storage. However, due to its distinctive operation mechanisms, it endures only the limited number of program/Erase cycles. So, bad blocks are inevitably developed during the life time of the storage system. A bad block is a block that contains faulty bits that cannot be covered by ECC. In this paper, a novel in-field bad block detection scheme is proposed. Through simple write verifications, the proposed bad block detector finds bad blocks in real-time, and ensures that written data is reliable. The detection method includes neither costly data-mirroring nor complex ECC processing, but it requires an additional detection module of which size is less than 0.15% of the controller size.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127856656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hardware accelerator for low-power sensor hub MCU to process sensor fusion algorithm 硬件加速器的低功耗传感器集线器单片机处理传感器融合算法
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401782
Minkwan Kee, Hyun-Su Seon, Sung-Taek Kwon, Jongsung Lee, Gi-Ho Park
{"title":"Hardware accelerator for low-power sensor hub MCU to process sensor fusion algorithm","authors":"Minkwan Kee, Hyun-Su Seon, Sung-Taek Kwon, Jongsung Lee, Gi-Ho Park","doi":"10.1109/ISOCC.2015.7401782","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401782","url":null,"abstract":"Recently, a sensor hub SoC (system on chip), a specialized MCU (microcontroller unit) to process data delivered by various sensors, has been adopted in mobile and wearable devices. This paper presents a hardware accelerator to detect the orientation of movement based on the 6-axis sensors. The structure of the accelerator is designed based on the profiling of a sensor fusion algorithm. The performance evaluation shows that the proposed accelerator can improve execution time by more than 100%.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121425005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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