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2015 International SoC Design Conference (ISOCC)最新文献

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A static bidirectional learning technique to accelerate test pattern generation 一种静态双向学习技术，用于加速测试模式的生成
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401692
J. Pan, Kuen-Wei Yeh, Jiun-Lang Huang
{"title":"A static bidirectional learning technique to accelerate test pattern generation","authors":"J. Pan, Kuen-Wei Yeh, Jiun-Lang Huang","doi":"10.1109/ISOCC.2015.7401692","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401692","url":null,"abstract":"Learning is a very effective technique to speed up the test pattern generation process. In this paper, we propose a static bidirectional learning technique that significantly increases the number of learned implications. The proposed bidirectional learning is integrated into PODEM. Experiment results show that, compared to previous static learning, in average the number of learned implications increases by 10%, and the CPU times are reduced by 24%.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130558491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Loop stability compensation technique for continuous-time common-mode feedback circuits 连续共模反馈电路的回路稳定性补偿技术
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401737
Young‐Kyun Cho, B. Park
{"title":"Loop stability compensation technique for continuous-time common-mode feedback circuits","authors":"Young‐Kyun Cho, B. Park","doi":"10.1109/ISOCC.2015.7401737","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401737","url":null,"abstract":"A loop stability compensation technique for continuous-time common-mode feedback (CMFB) circuits is presented. A Miller capacitor and nulling resistor in the compensation network provide a reliable and stable operation of the fully-differential operational amplifier without any performance degradation. The amplifier is designed in a 130 nm CMOS technology, achieves simulated performance of 57 dB open loop DC gain, 1.3-GHz unity-gain frequency and 65° phase margin. Also, the loop gain, bandwidth and phase margin of the CMFB are 51 dB, 27 MHz, and 76°, respectively.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126889149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A new built-in redundancy analysis algorithm based on multiple memory blocks 一种新的基于多存储块的内置冗余分析算法
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401691
Jooyoung Kim, Keewon Cho, Woosung Lee, Sungho Kang
{"title":"A new built-in redundancy analysis algorithm based on multiple memory blocks","authors":"Jooyoung Kim, Keewon Cho, Woosung Lee, Sungho Kang","doi":"10.1109/ISOCC.2015.7401691","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401691","url":null,"abstract":"With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS image sensor with non-memory capacitor two-step single slope ADC for high frame rate 一种具有非记忆电容的CMOS图像传感器，用于高帧率的两步单斜率ADC
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401723
Junan Lee, Jongyeon Lee, J. Burm
{"title":"A CMOS image sensor with non-memory capacitor two-step single slope ADC for high frame rate","authors":"Junan Lee, Jongyeon Lee, J. Burm","doi":"10.1109/ISOCC.2015.7401723","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401723","url":null,"abstract":"This paper proposes a column-parallel two-step Single-Slope Analog-to-Digital Converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). The total power consumption is 72 mW from supply voltages of 2.8 V(analog) and 1.5 V (digital). The Figure of Merit (FoM) is 2.01 [e-nJ].","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121664828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-noise and wide-bandwidth transimpedacne amplifier design for bionanopore applications 一种用于生物纳米孔应用的低噪声、宽带宽传输放大器设计
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401720
J. Yun, Jungsuk Kim, Jong-Bum Park
{"title":"A low-noise and wide-bandwidth transimpedacne amplifier design for bionanopore applications","authors":"J. Yun, Jungsuk Kim, Jong-Bum Park","doi":"10.1109/ISOCC.2015.7401720","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401720","url":null,"abstract":"This paper presents a low-noise and wide-bandwidth transimpedance amplifier for bionanopore applications. Using a capacitive-feedback transimpedance amplifier for a headstage, the input-referred noise is drastically reduced, which enables one to accurately monitor DNA translocation. To achieve a wide bandwidth, an intermediator-and-differentiator structure and a split-resistor technique are proposed in this work.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121788769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A scan segment skip technique for low power test 一种用于低功耗测试的扫描段跳过技术
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401669
Hayoung Lee, JunKyu Lee, Hyunyul Lim, Sungho Kang
{"title":"A scan segment skip technique for low power test","authors":"Hayoung Lee, JunKyu Lee, Hyunyul Lim, Sungho Kang","doi":"10.1109/ISOCC.2015.7401669","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401669","url":null,"abstract":"Excessive power consumption during testing has been one of the most important issues from the exponential advance in semiconductor manufacturing technology. In this paper, a scan segment skip technique is proposed to reduce power consumption by skipping segments that don't need scan in/out processes. Also, a new pattern merge algorithm is proposed for maximizing power reduction ratio. Experimental results show that the proposed technique efficiently reduces test power consumption with the minimal impact on area overhead.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of 270 Mbps 2×2 MIMO-OFDM system for video streaming in internet of things 270 Mbps 2×2物联网视频流MIMO-OFDM系统设计
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401699
Minjoon Kim, J. Mun, Jaeseok Kim
{"title":"Design of 270 Mbps 2×2 MIMO-OFDM system for video streaming in internet of things","authors":"Minjoon Kim, J. Mun, Jaeseok Kim","doi":"10.1109/ISOCC.2015.7401699","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401699","url":null,"abstract":"This paper presents designing of wireless local area network (WLAN) modem for video streaming in internet of things (IoT). Many concepts based on video streaming are introduced recently, and these systems need communication modem supporting high throughput for transmission of high quality of video. In this paper, WLAN modem using 2×2 multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) technique is designed. The proposed WLAN modem can support max 270 Mbps.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131753784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Calibration of interconnect corners using on-chip ring oscillators 使用片上环形振荡器校准互连角
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401698
Daijoon Hyun, Youngsoo Shin
{"title":"Calibration of interconnect corners using on-chip ring oscillators","authors":"Daijoon Hyun, Youngsoo Shin","doi":"10.1109/ISOCC.2015.7401698","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401698","url":null,"abstract":"Interconnect corners should accurately reflect actual interconnect in silicon to ensure proper design signoff. On-chip ring oscillator (ROSC) based calibration of interconnect corners is proposed. It comprises extraction of ROSC delay as a function of interconnect resistance and capacitance, projection of measured delay on that function, and identifying how existing corners should be adjusted. Simulation using a new calibrated corner demonstrates an excellent match with measurement in 14-nm test chips.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131812204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An energy efficient multi-scale retinex algorithm based on the ratio of saturated regions 一种基于饱和区域比例的高能效多尺度retinex算法
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401704
C. Jang, Young Hwan Kim
{"title":"An energy efficient multi-scale retinex algorithm based on the ratio of saturated regions","authors":"C. Jang, Young Hwan Kim","doi":"10.1109/ISOCC.2015.7401704","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401704","url":null,"abstract":"This paper proposes an image enhancement technique that adjusts the luminance of an input image depending on the image characteristics. First, the proposed method classifies the input image into three types based on the ratio of saturated region. After the classification, the enhancement process is adaptively performed depending on the classified image type to improve the image quality and reduce the power consumption. In the enhancement process, the proposed method reduces computational complexity for the low power consumption when calculating the illumination. Thus, the proposed method has an advantage of effectively reducing the power consumption as much as possible, while improving the output image quality. The experimental results showed that the proposed method successfully reduced the power consumption by up to 90.4% while increasing the enhancement performance measure by up to 73% and obtaining the highest subjective scores compared to the benchmark methods.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130911629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Special-purpose hardware architecture for neuromorphic computing 用于神经形态计算的专用硬件架构
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401792
Byungik Ahn
{"title":"Special-purpose hardware architecture for neuromorphic computing","authors":"Byungik Ahn","doi":"10.1109/ISOCC.2015.7401792","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401792","url":null,"abstract":"In this paper, we describe a special-purpose hardware architecture for neural network simulation systems called neuron machine that can be used effectively for neuromorphic simulations. A neuron machine system consists of a single digital hardware neuron, which is designed as a large-scale fine-grained pipelined circuit, and a memory unit called network unit. By using extensive pipelining and a large number of memories, neuron machine system exploits a large amount of the parallelism inherent in neural networks while retaining the flexibilities of network topology. As an example of the proposed architecture, a simulation system for the networks of biologically realistic Hodgkin-Huxley neurons capable of complex synaptic features such as spike-timing dependent plasticity and dynamic synapse, is implemented on a field-programmable gate array (FPGA). Our system implemented on a single mid-range FPGA chip computed at a speedup of 1200x over a CPU-based system.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"38 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133479471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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