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2015 International SoC Design Conference (ISOCC)最新文献

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Electrothermal analysis with generalized boundary conditions 具有广义边界条件的电热分析
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-03 DOI: 10.1109/ISOCC.2015.7401689
Suhyeong Choi, Seongbo Shim, Youngsoo Shin
{"title":"Electrothermal analysis with generalized boundary conditions","authors":"Suhyeong Choi, Seongbo Shim, Youngsoo Shin","doi":"10.1109/ISOCC.2015.7401689","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401689","url":null,"abstract":"Electrothermal analogy allows a resistive or RC network to be used for simple and convenient thermal analysis; however, it is only valid when heat transfer is purely convective or conductive. We investigate the analogy when a chip's operating environment is not purely convective, e.g. convective atmosphere with some source of heat flux, which is typically the practical case. We mathematically show that the analogy can be extended to such an environment, but with some modifications in a resistive network.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123458616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memristor cellular automata through belief propagation inspired algorithm 忆阻器元胞自动机的信念传播启发算法
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401793
Jacopo Secco, Marco Farina, D. Demarchi, F. Corinto
{"title":"Memristor cellular automata through belief propagation inspired algorithm","authors":"Jacopo Secco, Marco Farina, D. Demarchi, F. Corinto","doi":"10.1109/ISOCC.2015.7401793","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401793","url":null,"abstract":"The development of neuromorphic systems has increased in pace in the past years since the birth of industrial samples of memristors. In addition to developing the general technology, a strong interest in generating new applications for memristive systems is emerging. In this paper we present a Cellular Automata (CA) that works exploiting the Belief Propagation Inspired (BPI) algorithm. To foster and to prove the the equivalence among the two systems a image processing example is introduced.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115363291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
20nm High-K metal gate heterogeneous 64-bit quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor 20nm High-K金属栅异构64位四核cpu和六核GPU，用于高性能节能的移动应用处理器
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401760
Hoi-Jin Lee, Youngmin Shin, Sung-il Bae, Min-su Kim, Kwangil Kim, Jungyul Pyo, Sunghee Yun, Jae-Cheol Son, Inyup Kang
{"title":"20nm High-K metal gate heterogeneous 64-bit quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor","authors":"Hoi-Jin Lee, Youngmin Shin, Sung-il Bae, Min-su Kim, Kwangil Kim, Jungyul Pyo, Sunghee Yun, Jae-Cheol Son, Inyup Kang","doi":"10.1109/ISOCC.2015.7401760","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401760","url":null,"abstract":"This paper presents a heterogeneous configuration of two 64-bit different target quad-core CPUs. To support both high-performance and high energy-efficiency depending on application requirements, two types of 64-bit quad-core CPUs are implemented in one mobile application processor. The first quad-core CPU provides the highest performance at the cost of reasonable power consumption. The second quad-core CPU manages most of non-peak workload with high energy efficiency. This paper addresses the design issues for 64-bit high-performance quad-core CPU and for low-power quad-core CPU. Our heterogeneous configuration of two 64-bit different target implementations can provide efficient power and performance for various mobile applications.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117058749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A compact 60 GHz LNA design with enhanced stability by layout technique in 65 nm CMOS 一个紧凑的60 GHz LNA设计，通过65纳米CMOS布局技术增强了稳定性
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401788
T. B. Kumar, Kaixue Ma, K. Yeo
{"title":"A compact 60 GHz LNA design with enhanced stability by layout technique in 65 nm CMOS","authors":"T. B. Kumar, Kaixue Ma, K. Yeo","doi":"10.1109/ISOCC.2015.7401788","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401788","url":null,"abstract":"The paper presents a broadband low noise amplifier emphasizing on stability improvement by layout techniques. The proposed LNA achieves a gain of 13.7 dB, a 3-dB bandwidth of 47.6 GHz to 67.1 GHz and a dc current consumption of 23 mA from a 1.2 V supply voltage. This work delivers +5.8 dBm and +9.6 dBm saturated output power with 10.3% and 16% peak PAE under a supply voltage of 1.2 V and 2.1 V, respectively, measured at 58 GHz. The proposed design is fabricated in a 65 nm CMOS process and occupies a die area of 0.24 mm2.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117199671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 10-b 10MS/s SAR ADC with power and accuracy control of the comparator 具有功率和精度控制比较器的10-b 10MS/s SAR ADC
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401729
B. S. Rikan, Dong-Hyeon Seo, Kangyoon Lee
{"title":"A 10-b 10MS/s SAR ADC with power and accuracy control of the comparator","authors":"B. S. Rikan, Dong-Hyeon Seo, Kangyoon Lee","doi":"10.1109/ISOCC.2015.7401729","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401729","url":null,"abstract":"This paper proposes a 10-b 10MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) structure using Vcm based capacitive digital-to-analog (CDAC). In the proposed capacitive DAC, switching is always straightforward and the MSB is decided without any switching energy. The input is sampled at the bottom plate of the CDAC as it provides better linearity. Comparator applies adaptive power control to reduce the power consumption. For further power reduction, the accuracy of the comparator for coarse and fine bits are different and the reconfigurable structure has been applied. A prototype ADC was implemented in CMOS 0.18μm technology. This structure consumed 330μW and achieved 58.9-dB SNDR and 66.5-dB SFDR at 10MS/s under a 1.8-V supply. The figure of merit (FOM) was 58fJ/conversion-step.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"54 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120916947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A switched-capacitor filter with a slew rate enhancement technique 一种采用摆率增强技术的开关电容滤波器
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401740
Chulkyu Park, Kichang Jang, Joongho Choi
{"title":"A switched-capacitor filter with a slew rate enhancement technique","authors":"Chulkyu Park, Kichang Jang, Joongho Choi","doi":"10.1109/ISOCC.2015.7401740","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401740","url":null,"abstract":"In this paper, a switched-capacitor filter with a slew rate enhancement circuit for wireless communication applications is designed. The type of the filter is chosen the 5th-order Elliptic lowpass filter to implement over 43dB of stopband attenuation at the 1.4 times frequency of passband. For direct conversion transceiver applications, the DC offset canceling circuit and programmable gain amplifier are included. The filter is fabricated in a 0.35-μm CMOS 2P4M technology. The power dissipation is 14.7mW for a single supply voltage of 3 V.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121065822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Distributed congestion control for ZigBee wireless multi-hop routers ZigBee无线多跳路由器的分布式拥塞控制
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401744
Bongsoo Kim, J. Song, Hanjin Cho
{"title":"Distributed congestion control for ZigBee wireless multi-hop routers","authors":"Bongsoo Kim, J. Song, Hanjin Cho","doi":"10.1109/ISOCC.2015.7401744","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401744","url":null,"abstract":"A representative communication standard of the Internet of Things(IoT) is a low cost ZigBee. ZigBee is suitable for using in a wireless sensor network. Because it operates based upon utilizing low power. However, if congestions occur in routers that make up the wireless multi-hop network, there can be a serious problem that the buffer of the routers overflows. In this paper, we propose a new algorithm that can be conserved the power to reduce the congestion that occurs in multi-hop wireless routers that make up the network using ZigBee. The results show that proposal algorithm's frame loss rate is 20% less than existing algorithm. Also power consumption gained the 12.5% through the problem how to make a group.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127124152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A review of recent research on mm-scale sensor systems 毫米级传感器系统的最新研究综述
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401659
Yoonmyung Lee
{"title":"A review of recent research on mm-scale sensor systems","authors":"Yoonmyung Lee","doi":"10.1109/ISOCC.2015.7401659","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401659","url":null,"abstract":"With continuous miniaturization of electronic systems, mm-scale sensors are emerging as a future sensor system platform. Recent advancements in mm-scale sensor design is reviewed in this paper. A mm-scale sensor platform and its characteristics are presented and prototype implementation for diverse applications on recent literature are introduced.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114435375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A modified TZ search algorithm for parallel integer motion estimation in high efficiency video coding 一种用于并行整数运动估计的改进TZ搜索算法
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401664
D. Nghia, Tae Sung Kim, Hyuk-Jae Lee, S. Chae
{"title":"A modified TZ search algorithm for parallel integer motion estimation in high efficiency video coding","authors":"D. Nghia, Tae Sung Kim, Hyuk-Jae Lee, S. Chae","doi":"10.1109/ISOCC.2015.7401664","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401664","url":null,"abstract":"This paper proposes a new integer motion estimation algorithm which is designed for hardware execution by modifying the conventional TZ search to allow parallel motion estimation of all PU partitions. The algorithm consists of three phases, the first, raster, and refinement searches. At beginning of each phase, the algorithm obtains the search points required by the original TZ search for all PU partitions in a CU. Then, all the search points are used for the estimation of the motion costs for all PUs and the best search points are selected for all PUs. Compare to the conventional TZ search algorithm, the proposed algorithm decreases BD-BR by 1.06%.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117083475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A supply-insensitive self-regulating CMOS ring oscillator 一种电源不敏感自调节CMOS环形振荡器
2015 International SoC Design Conference (ISOCC) Pub Date : 2015-11-01 DOI: 10.1109/ISOCC.2015.7401652
S. Harb, W. Eisenstadt
{"title":"A supply-insensitive self-regulating CMOS ring oscillator","authors":"S. Harb, W. Eisenstadt","doi":"10.1109/ISOCC.2015.7401652","DOIUrl":"https://doi.org/10.1109/ISOCC.2015.7401652","url":null,"abstract":"This paper presents a resistor-free self-regulating CMOS ring oscillator (RO) whose oscillation frequency is insensitive to supply noise variations. The proposed RO design achieves self-regulation by adopting a cross-coupled dual latch-based scheme; Proper custom device sizing of the cross-coupled latches can improve supply noise immunity and frequency stability compared to a simple inverter design. A Five-stage RO is designed and implemented as a test vehicle which shows > 40% improvement in reducing supply noise sensitivity with a maximum frequency of 1GHz and 0.7mW power consumption. The simulation results are obtained using the Spectre simulator based on digital CMOS 0.09μm process Technology.","PeriodicalId":311212,"journal":{"name":"2015 International SoC Design Conference (ISOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128275990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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