A compact 60 GHz LNA design with enhanced stability by layout technique in 65 nm CMOS

Abstract

The paper presents a broadband low noise amplifier emphasizing on stability improvement by layout techniques. The proposed LNA achieves a gain of 13.7 dB, a 3-dB bandwidth of 47.6 GHz to 67.1 GHz and a dc current consumption of 23 mA from a 1.2 V supply voltage. This work delivers +5.8 dBm and +9.6 dBm saturated output power with 10.3% and 16% peak PAE under a supply voltage of 1.2 V and 2.1 V, respectively, measured at 58 GHz. The proposed design is fabricated in a 65 nm CMOS process and occupies a die area of 0.24 mm2.