2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)最新文献

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Design of an input-queued ATM switch supporting multicast and research on its scheduling policy 一种支持组播的输入排队ATM交换机的设计及其调度策略研究
Zhai Mingyu, Zhao Qi, Luo Junzhou, Gu Guanqun
{"title":"Design of an input-queued ATM switch supporting multicast and research on its scheduling policy","authors":"Zhai Mingyu, Zhao Qi, Luo Junzhou, Gu Guanqun","doi":"10.1109/HPSR.2001.923656","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923656","url":null,"abstract":"Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for unicast input-queued ATM switches and also applied in commerce. But the goal of the research on scheduling algorithms for multicast input-queued ATM switches only focuses on providing high throughput and inadvertently ignoring its undesired effects on QoS of the multicast traffic. In this paper we present a design scheme of input-queued ATM switches supporting multicast and corresponding scheduling algorithm, referred to as multicast longest normalized queue first (MLNQF). The MLNQF algorithm has the characteristics of improving throughput, satisfying QoS requirements and providing service fairly.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126140299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the convergence of path vector routing protocols 路径矢量路由协议的收敛性
J. Sobrinho
{"title":"On the convergence of path vector routing protocols","authors":"J. Sobrinho","doi":"10.1109/HPSR.2001.923649","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923649","url":null,"abstract":"This work is motivated by previously reported experimental results on the delayed convergence of the border gateway protocol (BGP), which is the standard for inter-domain routing in the Internet. BGP is a path vector protocol. We investigate the convergence properties of path vector protocols and, in particular, their alleged effectiveness in dealing with the count-to-infinity problem that plagues conventional distance vector protocols. We assume synchronous operation of the protocols, and we study the cases when a destination comes up, the network topology changes while preserving connectedness, and a destination goes down. It is known that path vector protocols do not count to infinity. We show that they may still count to the length of the longest possible path in the network, when a destination goes down. On the other hand, when a destination comes up or the topology of the network changes, convergence time depends on the diameter of the network. The length of the longest path in a network may differ substantially from its diameter. In order to further understand the convergence properties of path vector protocols, we simulated their behavior over random graphs. We verified that path vector protocols converge much more quickly when a destination comes up than when it goes down.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fair, efficient and low-latency packet scheduling using nested deficit round robin 公平,高效和低延迟数据包调度使用嵌套赤字轮询
S. Kanhere, H. Sethu
{"title":"Fair, efficient and low-latency packet scheduling using nested deficit round robin","authors":"S. Kanhere, H. Sethu","doi":"10.1109/HPSR.2001.923594","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923594","url":null,"abstract":"In the emerging high-speed integrated-services packet-switched networks, packet scheduling algorithms in switches and routers play a critical role in providing the quality of-service (QoS) guarantees required by many applications. We present a new scheduling discipline called nested deficit round robin (Nested-DRR), which is fair, efficient and in addition has a low latency bound. Nested-DRR splits each DRR round into one or more smaller rounds, within each of which we run a modified version of the DRR scheduling discipline. In this paper, we analytically prove that Nested-DRR results in a significant improvement in the latency bound in comparison to DRR, and in addition preserves the good properties of DRR such as the per-packet work complexity of O(1). Nested DRR also has the same relative fairness bound as DRR.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122862404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
A traffic control mechanism based on the load of output ports in an ATM switch 一种基于ATM交换机输出端口负载的流量控制机制
Hong-soon Nam, D. Choi, Y. An, Woo-Seep Lee, Kyu-Ouk Lee, Kwon-Cheol Park
{"title":"A traffic control mechanism based on the load of output ports in an ATM switch","authors":"Hong-soon Nam, D. Choi, Y. An, Woo-Seep Lee, Kyu-Ouk Lee, Kwon-Cheol Park","doi":"10.1109/HPSR.2001.923604","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923604","url":null,"abstract":"In this paper, we propose a traffic control mechanism for ATM switches consisting of common buffered switch fabrics without buffer separation. The proposed mechanism allocates the rate of incoming traffic into switch fabrics according to the load of output ports. In the method, an egress line interface module (LIM) computes the available bandwidth (ABW) for each connection of non-real time traffic based on the load of the output port. The egress LIM sends back the ABW to ingress LIMs for each connection. According to the ABW, the ingress LIMs schedule the incoming traffic into switch fabrics of each connection. We also propose a rate-based cell-scheduling algorithm for the proposed mechanism. The proposed mechanism has been implemented by using FPGAs in the ACE256 ATM switch.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115294495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling high-speed shared-memory switch fabric buffers 扩展高速共享内存交换机结构缓冲区
M. Hegde, M. Naraghi-Pour
{"title":"Scaling high-speed shared-memory switch fabric buffers","authors":"M. Hegde, M. Naraghi-Pour","doi":"10.1109/HPSR.2001.923647","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923647","url":null,"abstract":"A novel approach is presented for expanding the buffer size in a shared memory switch. Utilizing this two-tier buffering mechanism we present a two-level scheduling algorithm whose complexity is considerably lower than that of purely input scheduling algorithms. Furthermore, this approach easily provides differentiated qualities of service to different traffic classes while maintaining high throughput across the switch fabric.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A terabit electro-optical Clos switch architecture 一种太比特电光开关结构
F. Liotopoulos
{"title":"A terabit electro-optical Clos switch architecture","authors":"F. Liotopoulos","doi":"10.1109/HPSR.2001.923644","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923644","url":null,"abstract":"The continuously growing user demands for fast and reliable switching of multi-services calls for the development of high-capacity, scalable core switch architectures. Multi-terabit (Tbps) switches can be effectively developed by combining electrical and optical components and technologies. Switches based on three-stage Clos (1953) networks are very attractive due to their modularity, scalability and fault-tolerance. We present and analyze a modular, multi-Tbps, three-stage Clos switch architecture, based on a two-level hierarchy of optical cross-connects, which can be implemented with arrayed waveguide filters (AWGFs) and optical delay fibers (ODFs). More \"intelligent\" switch logic, such as resource management functions, call-admission control, congestion and traffic control, routing, cell-header processing, etc. can be more efficiently done in electronics. The capacity of the proposed switch can scale up to 32 Tbps with 8/spl times/8 AWGFs and up to half a Pbps with 16/spl times/16 AWGFs. The internal cell blocking of the switch, its throughput latency and latency distribution is evaluated by simulation.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129320025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An improved PIM-SM tree recovery algorithm 一种改进的PIM-SM树恢复算法
T. Cicic, S. Gjessing, Oivind Kure
{"title":"An improved PIM-SM tree recovery algorithm","authors":"T. Cicic, S. Gjessing, Oivind Kure","doi":"10.1109/HPSR.2001.923658","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923658","url":null,"abstract":"Multicast tree recovery in protocol independent multicast-sparse mode (PIM-SM) networks is initiated by state changes in the underlying unicast routing protocol. A substantial part of the subsequent data loss can be attributed to the non-reductive events, e.g. link addition. We propose and evaluate an improvement to the standard PIM-SM recovery procedure, showing that the data loss can be significantly decreased regardless of the topology and session parameters.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129341553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Use of FEC coding for real-time transport on ATM networks 在ATM网络上使用FEC编码进行实时传输
R. Kurceren, J. Modestino
{"title":"Use of FEC coding for real-time transport on ATM networks","authors":"R. Kurceren, J. Modestino","doi":"10.1109/HPSR.2001.923603","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923603","url":null,"abstract":"The use of forward error-control (FEC) coding has emerged as a promising approach for real-time transport over ATM networks for cell-loss recovery. The use of an FEC-based transport protocol over networks with bandwidth constraints, however, is not obvious since FEC coding introduces an overhead which can possibly cause additional cell losses which, furthermore, tend to occur in bursts. In this work, an overall performance evaluation of FEC coding is provided by incorporating the effects of channel coding on the cell-loss characteristics of the network. It is shown that FEC coding with proper selection of channel coding rate can significantly improve the throughput at a multiplexer even under correlated cell-loss situations. We also develop and illustrate an information-theoretic approach for incorporating the effects of FEC coding into well-established queueing theory calculations. This is achieved by solving separately the channel-coding problem for the modeled transmission channel and the queueing problem for the network. The performance of some specific coding designs are shown to approach the information-theoretic predictions with increasing complexity and/or delay.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123862001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A processor based high-speed longest prefix match search engine 基于处理器的高速最长前缀匹配搜索引擎
M. Kobayashi, T. Murase
{"title":"A processor based high-speed longest prefix match search engine","authors":"M. Kobayashi, T. Murase","doi":"10.1109/HPSR.2001.923638","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923638","url":null,"abstract":"This paper describes a new IP forwarding table search method that can be implemented on a general-purpose processor with a high-speed cache memory. It uses an efficient small data structure to store an IP forwarding table in the cache memory by exploiting a characteristic of the IP address prefixes of forwarding tables in the Internet backbone. At the particular level of the prefix-tree, the number of the prefixes below most of the nodes is very small. The method enables a general-purpose 500-MHz processor equipped with a 512-KB internal cache to perform searches at the wire-speed of a 2.4-Gb/sec link.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116263582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel ultra high-speed multi-layer table lookup method using TCAM for differentiated services in the Internet 一种基于TCAM的超高速多层表查找方法
M. Uga, K. Shiomoto
{"title":"A novel ultra high-speed multi-layer table lookup method using TCAM for differentiated services in the Internet","authors":"M. Uga, K. Shiomoto","doi":"10.1109/HPSR.2001.923639","DOIUrl":"https://doi.org/10.1109/HPSR.2001.923639","url":null,"abstract":"This paper proposes ultra high-speed multi-layer table lookup method using ternary content-addressable memory (TCAM) for an ultra high-speed policy-based packet forwarding engine. It can store very wide policy rules in TCAM, whose width is limited. For IP version 6, policy rules could be 304 bits wide. This method enables us to use commercially available TCAM for multi-layer table lookups, and thus build an ultra high-speed packet forwarding engine for differentiated services in the Internet.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122949976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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