{"title":"扩展高速共享内存交换机结构缓冲区","authors":"M. Hegde, M. Naraghi-Pour","doi":"10.1109/HPSR.2001.923647","DOIUrl":null,"url":null,"abstract":"A novel approach is presented for expanding the buffer size in a shared memory switch. Utilizing this two-tier buffering mechanism we present a two-level scheduling algorithm whose complexity is considerably lower than that of purely input scheduling algorithms. Furthermore, this approach easily provides differentiated qualities of service to different traffic classes while maintaining high throughput across the switch fabric.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Scaling high-speed shared-memory switch fabric buffers\",\"authors\":\"M. Hegde, M. Naraghi-Pour\",\"doi\":\"10.1109/HPSR.2001.923647\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel approach is presented for expanding the buffer size in a shared memory switch. Utilizing this two-tier buffering mechanism we present a two-level scheduling algorithm whose complexity is considerably lower than that of purely input scheduling algorithms. Furthermore, this approach easily provides differentiated qualities of service to different traffic classes while maintaining high throughput across the switch fabric.\",\"PeriodicalId\":308964,\"journal\":{\"name\":\"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HPSR.2001.923647\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2001.923647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel approach is presented for expanding the buffer size in a shared memory switch. Utilizing this two-tier buffering mechanism we present a two-level scheduling algorithm whose complexity is considerably lower than that of purely input scheduling algorithms. Furthermore, this approach easily provides differentiated qualities of service to different traffic classes while maintaining high throughput across the switch fabric.