{"title":"A terabit electro-optical Clos switch architecture","authors":"F. Liotopoulos","doi":"10.1109/HPSR.2001.923644","DOIUrl":null,"url":null,"abstract":"The continuously growing user demands for fast and reliable switching of multi-services calls for the development of high-capacity, scalable core switch architectures. Multi-terabit (Tbps) switches can be effectively developed by combining electrical and optical components and technologies. Switches based on three-stage Clos (1953) networks are very attractive due to their modularity, scalability and fault-tolerance. We present and analyze a modular, multi-Tbps, three-stage Clos switch architecture, based on a two-level hierarchy of optical cross-connects, which can be implemented with arrayed waveguide filters (AWGFs) and optical delay fibers (ODFs). More \"intelligent\" switch logic, such as resource management functions, call-admission control, congestion and traffic control, routing, cell-header processing, etc. can be more efficiently done in electronics. The capacity of the proposed switch can scale up to 32 Tbps with 8/spl times/8 AWGFs and up to half a Pbps with 16/spl times/16 AWGFs. The internal cell blocking of the switch, its throughput latency and latency distribution is evaluated by simulation.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2001.923644","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The continuously growing user demands for fast and reliable switching of multi-services calls for the development of high-capacity, scalable core switch architectures. Multi-terabit (Tbps) switches can be effectively developed by combining electrical and optical components and technologies. Switches based on three-stage Clos (1953) networks are very attractive due to their modularity, scalability and fault-tolerance. We present and analyze a modular, multi-Tbps, three-stage Clos switch architecture, based on a two-level hierarchy of optical cross-connects, which can be implemented with arrayed waveguide filters (AWGFs) and optical delay fibers (ODFs). More "intelligent" switch logic, such as resource management functions, call-admission control, congestion and traffic control, routing, cell-header processing, etc. can be more efficiently done in electronics. The capacity of the proposed switch can scale up to 32 Tbps with 8/spl times/8 AWGFs and up to half a Pbps with 16/spl times/16 AWGFs. The internal cell blocking of the switch, its throughput latency and latency distribution is evaluated by simulation.