2016 IEEE High Performance Extreme Computing Conference (HPEC)最新文献_第5页

Systems design of cybersecurity in embedded systems 嵌入式系统中的网络安全系统设计

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761615

M. Vai, David Whelihan, Nicholas Evancich, K. Kwak, Jason H. Li, M. Britton, J. Foley, Michael Lynch, Douglas Schafer, J. DeMatteis

引用次数: 8

Optimizing communication for a 2D-partitioned scalable BFS 优化二维分区可扩展BFS的通信

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761596

Jeffrey S. Young, J. Romera, Matthias Hauck, H. Fröning

引用次数: 3

KNN in the Jaccard space Jaccard空间中的KNN

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761587

Ming Ouyang

引用次数: 5

BigDAWG polystore query optimization through semantic equivalences 通过语义等价的BigDAWG多存储查询优化

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761584

Zuohao She, Surabhi Ravishankar, Jennie Duggan

引用次数: 36

Benchmarking SciDB data import on HPC systems 在HPC系统上对SciDB数据导入进行基准测试

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761617

S. Samsi, L. Brattain, W. Arcand, David Bestor, Bill Bergeron, C. Byun, V. Gadepally, M. Hubbell, Michael Jones, Anna Klein, P. Michaleas, Lauren Milechin, J. Mullen, Andrew Prout, Antonio Rosa, Charles Yee, J. Kepner, A. Reuther

{"title":"Benchmarking SciDB data import on HPC systems","authors":"S. Samsi, L. Brattain, W. Arcand, David Bestor, Bill Bergeron, C. Byun, V. Gadepally, M. Hubbell, Michael Jones, Anna Klein, P. Michaleas, Lauren Milechin, J. Mullen, Andrew Prout, Antonio Rosa, Charles Yee, J. Kepner, A. Reuther","doi":"10.1109/HPEC.2016.7761617","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761617","url":null,"abstract":"SciDB is a scalable, computational database management system that uses an array model for data storage. The array data model of SciDB makes it ideally suited for storing and managing large amounts of imaging data. SciDB is designed to support advanced analytics in database, thus reducing the need for extracting data for analysis. It is designed to be massively parallel and can run on commodity hardware in a high performance computing (HPC) environment. In this paper, we present the performance of SciDB using simulated image data. The Dynamic Distributed Dimensional Data Model (D4M) software is used to implement the benchmark on a cluster running the MIT SuperCloud software stack. A peak performance of 2.2M database inserts per second was achieved on a single node of this system. We also show that SciDB and the D4M toolbox provide more efficient ways to access random sub-volumes of massive datasets compared to the traditional approaches of reading volumetric data from individual files. This work describes the D4M and SciDB tools we developed and presents the initial performance results. This performance was achieved by using parallel inserts, a in-database merging of arrays as well as supercomputing techniques, such as distributed arrays and single-program-multiple-data programming.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134562724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Parallel motion estimation and GPU-based fast coding unit splitting mechanism for HEVC 并行运动估计和基于gpu的HEVC快速编码单元分割机制

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761586

Yih-Chuan Lin, Shang-Che Wu

引用次数: 5

Benchmarking the graphulo processing framework graphulo处理框架的基准测试

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761640

T. Weale, V. Gadepally, D. Hutchison, J. Kepner

{"title":"Benchmarking the graphulo processing framework","authors":"T. Weale, V. Gadepally, D. Hutchison, J. Kepner","doi":"10.1109/HPEC.2016.7761640","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761640","url":null,"abstract":"Graph algorithms have wide applicablity to a variety of domains and are often used on massive datasets. Recent standardization efforts such as the GraphBLAS specify a set of key computational kernels that hardware and software developers can adhere to. Graphulo is a processing framework that enables GraphBLAS kernels in the Apache Accumulo database. In our previous work, we have demonstrated a core Graphulo operation called TableMult that performs large-scale multiplication operations of database tables. In this article, we present the results of scaling the Graphulo engine to larger problems and scalablity when a greater number of resources is used. Specifically, we present two experiments that demonstrate Graphulo scaling performance is linear with the number of available resources. The first experiment demonstrates cluster processing rates through Graphulo's TableMult operator on two large graphs, scaled between 217 and 219 vertices. The second experiment uses TableMult to extract a random set of rows from a large graph (219 nodes) to simulate a cued graph analytic. These benchmarking results are of relevance to Graphulo users who wish to apply Graphulo to their graph problems.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127076870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Cross-institutional research cyberinfrastructure for data intensive science 数据密集型科学的跨机构研究网络基础设施

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761597

W. Lenhardt, Mike C. Conway, Erik Scott, B. Blanton, A. Krishnamurthy, M. Hadzikadic, M. Vouk, A. Wilson

引用次数: 5

Real-time, low-latency image processing with high throughput on a multi-core SoC 实时，低延迟的图像处理，在多核SoC上具有高吞吐量

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761645

B. Ramesh, A. George, H. Lam

引用次数: 2

On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA 片上存储器在三维存储器集成FPGA上实现二维FFT的高效数据布局

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761606

Shreyas G. Singapura, R. Kannan, V. Prasanna

{"title":"On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA","authors":"Shreyas G. Singapura, R. Kannan, V. Prasanna","doi":"10.1109/HPEC.2016.7761606","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761606","url":null,"abstract":"3D memories are becoming viable solutions for the memory wall problem and meeting the bandwidth requirements of memory intensive applications. The high bandwidth provided by 3D memories does not translate to a proportional increase in performance for all applications. For an application such as 2D FFT with strided access patterns, the data layout of the memory has a significant impact on the total execution time of the implementation. In this paper, we present a data layout for 2D FFT on 3D memory integrated FPGA that is both on-chip memory efficient as well as throughput-optimal. Our data layout ensures that consecutive accesses to 3D memory are sufficiently interleaved among layers and vaults to absorb latency due to activation overheads for both sequential (Row FFT) and strided (Column FFT) accesses. The current state-of-the-art implementation on 3D memory requires O(√cN) on-chip memory to reduce the strided accesses and achieve maximum bandwidth for an N × N FFT problem size and c columns in a 3D memory bank row. Our proposed data layout optimizes the throughput of both the Row FFT and Column FFT phases of 2D FFT with O(N) on-chip memory for the same problem size and memory parameters without decreasing the memory bandwidth thereby achieving a √c× reduction in on-chip memory. On architectures with limited on-chip memory, our data layout achieves 2× to 4× improvement in execution time compared with the state-of-art 2D FFT implementation on 3D memory.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"204 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113998567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3