{"title":"Distributed and configurable architecture for neuromorphic applications on heterogeneous cluster","authors":"Khadeer Ahmed, Qinru Qiu, M. Tamhankar","doi":"10.1109/HPEC.2016.7761598","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761598","url":null,"abstract":"With the proliferation of application specific accelerators, the use of heterogeneous clusters is rapidly increasing. Consisting of processors with different architectures, a heterogeneous cluster aims at providing different performance and cost tradeoffs for different types of workloads. In order to achieve peak performance, software running on heterogeneous cluster needs to be designed carefully to provide enough flexibility to explore its variety. We propose a design methodology to modularize complex software applications with data dependencies. The software application designed in this way have the flexibility to be reconfigured for different hardware platforms to facilitate resource management, and features high scalability and parallelism. Using a neuromorphic application as a case study, we present the concept of modularization and discuss the management, scheduling and communication of the modules. We also present experimental results demonstrating the improvements and effects of system scaling on throughput.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On SDN-based extreme-scale networks","authors":"Haitham Ghalwash, Chun-Hsi Huang","doi":"10.1109/HPEC.2016.7761621","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761621","url":null,"abstract":"Significant research effort has been made on formulating new topologies to meet the requirements of current and future large-scale data centers. Nowadays data centers may include tens of thousands of servers, leading to an urgent need for higher bandwidth, better reliability, easier management and lower latency. This paper investigates the potential of using software-defined networks (SDNs) in Extreme scale systems, which are required for future data centers when scaling up to the Exascale level. SDN is the new trend for efficient traffic control and network management. We investigate the SDN-based behavior and performance of two widely used topologies in large-scale data centers, namely Fat-Tree and BCube, using different network scales, traffic loads and traffic patterns. Experimental results based on such performance metrics as delay, jitter and packet drops have indicated that the BCube-like topology outperforms the Fat-Tree topology in small-scale networks, while the Fat-Tree performs better as the network scales up.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121822436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A hardware design for in-brain neural spike sorting","authors":"Yinan Liu, Jiayi Sheng, M. Herbordt","doi":"10.1109/HPEC.2016.7761590","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761590","url":null,"abstract":"Neural spike sorting is used to classify neural spike signals based on neuron type and so is an essential step in decoding brain signals. Because of its computational complexity, spike sorting is generally carried out offline or, at least, using a transmitted signal. In contrast, in-brain spike sorting would reduce the data that needs to be transmitted by orders of magnitude with a corresponding reduction in transmission power. This would enable real-time wireless neural recordings. In this paper, we design and characterize a hardware prototype for in-brain spike sorting. Our design is able to reduce the wireless transmission power by a factor of over 200 over direct transmission. Also, compared with the current state-of-the-art, our design increases the sorting accuracy from 75% to 93% while remaining within hard constraints for power, power density, and real-time processing.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123511616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Brayford, C. Bernau, Carla Guillén, C. Navarrete
{"title":"Node level power measurements on a petaflop system","authors":"D. Brayford, C. Bernau, Carla Guillén, C. Navarrete","doi":"10.1109/HPEC.2016.7761631","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761631","url":null,"abstract":"The complexity and size of scientific and engineering challenges are continually increasing to the point where they are approaching exascale computing. One of the main challenges is to be able to run scientific software applications on these extremely large systems in an energy efficient manner, as power consumption will become one of the dominant cost factors that will govern the next generation of large high performance computing data centers. In this paper, we present the results of node level power measurements on a petaflop HPC system.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The BigDawg monitoring framework","authors":"Peinan Chen, V. Gadepally, M. Stonebraker","doi":"10.1109/HPEC.2016.7761642","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761642","url":null,"abstract":"BigDAWG is a polystore database system designed to work with heterogenous data that may be stored in disparate database and storage engines. A central component of the BigDAWG polystore system is the ability to submit queries that may be executed in different data engines. This paper presents a monitoring framework for the BigDawg federated database system which maintains performance information on benchmark queries. As environmental conditions change, the monitoring framework updates existing performance information to match current conditions. Using this information, the monitoring system can determine the optimal query execution plan for similar incoming queries. We also describe a series of test queries that were run to assess whether the system correctly determines the optimal plans for such queries.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Pradelle, M. Baskaran, Thomas Henretty, Benoît Meister, A. Konstantinidis, R. Lethin
{"title":"Polyhedral compilation for energy efficiency","authors":"B. Pradelle, M. Baskaran, Thomas Henretty, Benoît Meister, A. Konstantinidis, R. Lethin","doi":"10.1109/HPEC.2016.7761595","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761595","url":null,"abstract":"In the last decade, the scope of software optimizations expanded to encompass energy consumption on top of the classical runtime minimization objective. In that context, several optimizations have been developed to improve the software energy efficiency. However, these optimizations commonly rely on long profiling steps and are often implemented as unstable runtime systems, which limits their applicability. We propose in this paper a new energy model and two associated energy optimizations that can be performed at compilation time, without having to profile the compiled programs. The model predicts the energy consumption of programs at compilation time using the precise software representation available in the polyhedral model. The energy model is then used at the core of two compiler optimizations to generate more efficient programs. The model and the two optimizations have been implemented in the R-Stream compiler.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125721611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Towards parallel implementation of associative inference for cogent confabulation","authors":"Zhe Li, Qinru Qiu, M. Tamhankar","doi":"10.1109/HPEC.2016.7761623","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761623","url":null,"abstract":"The superb efficiency and noise resilience of human cognizance comes from the extensive highly associative memory. For example, it is easy for human to recognize occluded or incomplete text images based on its context. Associative inference in the neocortex system is a concurrent process. Serial implementation of this concurrent process not only hinders its performance, but also limits the quality of recall. This paper investigates parallel implementation of associative inference using cogent confabulation model, which is a highly cross-dependent and cyclic knowledge network that supports probabilistic inference. By breaking the fixed processing order, which is typical in sequential processing, and introducing randomness generated from the race conditions in parallel processing, we do not only reduce the runtime, but also improve the accuracy. Further improvement can be achieved by scheduling the lexicon processing intermittently, which provides time for the changes to settle down. Using sentence construction as a case study, we demonstrate that the parallel implementation provides up to 93.4% reduction in computation time and 5% improvement in recall accuracy.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134559639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Nita, I. Stroia, L. Itu, C. Suciu, Viorel Mihalef, M. Datar, S. Rapaka, Puneet S. Sharma
{"title":"GPU accelerated, robust method for voxelization of solid objects","authors":"C. Nita, I. Stroia, L. Itu, C. Suciu, Viorel Mihalef, M. Datar, S. Rapaka, Puneet S. Sharma","doi":"10.1109/HPEC.2016.7761582","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761582","url":null,"abstract":"Solid voxelization represents the process of transforming a polygonal mesh into a voxel representation by associating each polygon of a mesh with the cells in the voxel grid. We introduce a novel approach for the voxelization of solid objects, designed for Graphics Processing Units (GPU). The method is based on a heuristic approach that computes an approximate distance field instead of using mesh surface normals or exact point-to-triangle distances. Two main steps are required: voxel marking and distance field computation. In the first step, each voxel is marked based on its location relative to the mesh (inside, outside of the domain or on its boundary), and, during the second step, a signed distance field is computed. Experiments focused on meshes encountered in medical imaging applications: a left ventricle and a coronary artery. The proposed method is found to be exceptionally robust as it is able to handle meshes with severe defects such as self intersections and holes. The GPU based implementation is on average 20 times faster than the multi-core CPU based implementation.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132631024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David K. Wittenberg, E. Kadrić, A. DeHon, J. Edwards, Jeffrey E. Smith, S. Chiricescu
{"title":"PERFECT case studies demonstrating order of magnitude reduction in power consumption","authors":"David K. Wittenberg, E. Kadrić, A. DeHon, J. Edwards, Jeffrey E. Smith, S. Chiricescu","doi":"10.1109/HPEC.2016.7761612","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761612","url":null,"abstract":"We propose three methods for reducing power consumption in high-performance FPGAs (field programmable gate arrays). We show that by using continuous hierarchy memory, lightweight checks, and lower chip voltage for near-threshold voltage computation, we can both reduce power consumption and increase reliability without a decrease in throughput. We have implemented these techniques in two different, realistic wide-area motion imagery algorithms on FPGAs. We demonstrated greatly improved performance/efficiency compared to two flight-tested platforms, getting up to a 250X reduction in power use (measured in giga operations per second per watt). This paper summarizes these two case studies.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132540453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. George, M. Herbordt, H. Lam, A. Lawande, Jiayi Sheng, Chen Yang
{"title":"Novo-G#: Large-scale reconfigurable computing with direct and programmable interconnects","authors":"A. George, M. Herbordt, H. Lam, A. Lawande, Jiayi Sheng, Chen Yang","doi":"10.1109/HPEC.2016.7761639","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761639","url":null,"abstract":"While High-Performance Computing is ever more pervasive and effective, computing capability is currently only a small fraction of what is needed. Three fundamental issues limiting performance are computational efficiency, power density, and communication latency. All of these issues are being addressed through increased heterogeneity, but the last in particular by integrating communication into the accelerator. This integration enables direct and programmable communication among compute components. Novo-G# is a large-scale FPGA-centric cluster being built to investigate and develop architectures, system and tool infrastructure, and applications for this model. In this report we discuss the motivation behind and particular objectives of Novo-G#, the work completed so far, the products of that work, and their potential impact. We end with a description of and an invitation to join the Novo-G# Forum, the project users group.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124280406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}