2016 IEEE High Performance Extreme Computing Conference (HPEC)最新文献

{"title":"Advantages to modeling relational data using hypergraphs versus graphs","authors":"Michael M. Wolf, A. Klinvex, Daniel M. Dunlavy","doi":"10.1109/HPEC.2016.7761624","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761624","url":null,"abstract":"Driven by the importance of relational aspects of data to decision-making, graph algorithms have been developed, based on simplified pairwise relationships, to solve a variety of problems. However, evidence has shown that hypergraphs-generalizations of graphs with (hyper)edges that connect any number of vertices-can better model complex, non-pairwise relationships in data and lead to better informed decisions. In this work, we compare graph and hypergraph models in the context of spectral clustering. For these problems, we demonstrate that hypergraphs are computationally more efficient and can better model complex, non-pairwise relationships for many datasets.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123889977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How naive is naive SpMV on the GPU?","authors":"M. Steinberger, Andreas Derler, Rhaleb Zayer, H. Seidel","doi":"10.1109/HPEC.2016.7761634","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761634","url":null,"abstract":"Sparse matrix vector multiplication (SpMV) is the workhorse for a wide range of linear algebra computations. In a serial setting, naive implementations for direct multiplication and transposed multiplication achieve very competitive performance. In parallel settings, especially on graphics hardware, it is widely believed that naive implementations cannot reach the performance of highly tuned parallel implementations and complex data formats. Most often, the cost for data conversion to these specialized formats as well as the cost for transpose operations are neglected, as they do not arise in all algorithms. In this paper, we revisit the naive implementation of SpMV for the GPU. Relying on recent advances in GPU hardware, such as fast hardware supported atomic operations and better cache performance, we show that a naive implementation can reach the performance of state-of-the-art SpMV implementations. In case the cost of format conversion and transposition cannot be amortized over many SpMV operations a naive implementation can even outperform state-of-the-art implementations significantly. Experimental results over a variety of data sets suggest that the adoption of the naive serial implementation to the GPU is not as inferior as it used to be on previous hardware generations. The integration of some naive strategies can potentially speed up state-of-the-art GPU SpMV implementations, especially in the transpose case.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123246186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hypervisor performance analysis for real-time workloads","authors":"Geoffrey Phi C. Tran, Yu-An Chen, D. Kang, J. Walters, S. Crago","doi":"10.1109/HPEC.2016.7761610","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761610","url":null,"abstract":"Virtualization has become a key technology used in modern data centers. What began as a tool for server consolidation and energy efficiency has grown into an enabler for cloud computing. Cloud computing has become an accepted best practice for data centers. Virtualization is also becoming a key component of embedded and real-time systems in automotive systems, game consoles, and industrial settings. Many applications that run on embedded systems are bound to hard real-time requirements, meaning that deadlines must be met. While hypervisor performance for non-real-time workloads has been well-documented, comparison of performance across hypervisors for real-time workloads has not been systematically studied. In this paper, we fill that gap by characterizing Xen (Credit and Real-Time-Deferrable-Server schedulers) and Wind River's low-latency KVM for hard real-time workloads in one and two virtual machine (VM) cases. We compare each hypervisor to a non-virtualized base system and evaluate the relative merits of each hypervisor for a number of synthetic workloads with a number of varying characteristics. When using a single VM, and therefore no resource contention, we find that all configurations are capable of completing over 99.8% of their jobs within their deadline. This demonstrates that a virtualized environment can support some real-time applications, such as those with relaxed constraints. We also find that Wind River's low-latency KVM and Xen-RTDS scheduler are capable of supporting hard real-time constraints over a variety of task set characteristics. However, a use case with multiple VMs creates a need for resource sharing. The sharing of resources results in contention between guests for usage of the said resources. When two VMs are present, the XenRTDS and tuned Xen-credit scheduler are superior to the other configurations. Furthermore, we find that the default Xen-credit scheduler provides poor support for hard real-time constraints, regardless of whether resource contention is present. However, by tuning the credit scheduler's timeslice parameter to benefit latency-sensitive tasks, we observe that the performance of the credit scheduler is indeed able to support hard real-time constraints for the given workloads in both single VM and two VM cases. These developments in real-time virtualization prove to be an exciting step towards real-time enabled clouds.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124628638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Kokkos/Qthreads task-parallel approach to linear algebra based graph analytics","authors":"Michael M. Wolf, H. Edwards, Stephen L. Olivier","doi":"10.1109/HPEC.2016.7761649","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761649","url":null,"abstract":"The Graph BLAS effort to standardize a set of graph algorithms building blocks in terms of linear algebra primitives promises to deliver high performing graph algorithms and greatly impact the analysis of big data. However, there are challenges with this approach, which our data analytics miniapp miniTri exposes. In this paper, we improve upon a previously proposed task-parallel approach to linear algebra-based miniTri formulation, addressing these challenges and describing a Kokkos/Qthreads task-parallel implementation that performs as well or slightly better than the highly optimized, baseline OpenMP data-parallel implementation.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121162521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cross-engine query execution in federated database systems","authors":"Ankush M. Gupta, V. Gadepally, M. Stonebraker","doi":"10.1109/HPEC.2016.7761648","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761648","url":null,"abstract":"We have developed a reference implementation of the BigDAWG system: a new architecture for future Big Data applications, guided by the philosophy that “one size does not fit all”. Such applications not only call for large-scale analytics, but also for real-time streaming support, smaller analytics at interactive speeds, data visualization, and cross-storage-system queries. The importance and effectiveness of such a system has been demonstrated in a hospital application using data from an intensive care unit (ICU). In this article, we describe the implementation and evaluation of the cross-system Query Executor. In particular, we focus on cross-engine shuffle joins within the BigDAWG system, and evaluate various strategies of computing them when faced with varying degrees of data skew.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122273608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unified and lightweight tasks and conduits: A high level parallel programming framework","authors":"Chao Liu, M. Leeser","doi":"10.1109/HPEC.2016.7761583","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761583","url":null,"abstract":"Computing platforms for high performance and parallel applications have changed rapidly during the past few years, from single to multiple cores, and from traditional Central Processing Units (CPUs) to hybrid systems which combine CPUs with accelerators such as Graphics Processing Units(GPUs), Intel Xeon Phi, etc. These developments bring more and more challenges to application developers, especially to maintain a high performance application across various platforms. To reduce development effort and improve portability of applications, we propose a high level parallel programming framework called Unified Tasks and Conduits (UTC). An application represented as multiple tasks can be mapped and run on available computing devices of the target platform in parallel. Through this framework, higher level application program structure is independent from lower level task execution, making it easy to port applications to different platforms. To support the framework, we have implemented a lightweight and flexible runtime system prototype, providing a set of utilities for users to conveniently create parallel applications to run on multicore systems or clusters. Our micro-benchmarks show that the runtime system introduces little overhead to implement tasks and conduits. Application tests show that UTC based programs can make use of available computing resources to do parallel processing efficiently while easing the job of the developer.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"101 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132185186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"cuSTINGER: Supporting dynamic graph algorithms for GPUs","authors":"Oded Green, David A. Bader","doi":"10.1109/HPEC.2016.7761622","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761622","url":null,"abstract":"cuSTINGER, a new graph data structure targeting NVIDIA GPUs is designed for streaming graphs that evolve over time. cuSTINGER enables algorithm designers greater productivity and efficiency for implementing GPU-based analytics, relieving programmers of managing memory and data placement. In comparison with static graph data structures, which may require transferring the entire graph back and forth between the device and the host memories for each update or require reconstruction on the device, cuSTINGER only requires transferring the updates themselves; reducing the total amount of data transferred. cuSTINGER gives users the flexibility, based on application needs, to update the graph one edge at a time or through batch updates. cuSTINGER supports extremely high update rates, over 1 million updates per second for mid-size batched with 10k updates and 10 million updates per second for large batches with millions of updates.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon photonic memory interconnect for many-core architectures","authors":"K. Wen, H. Guan, D. Calhoun, D. Donofrio, J. Shalf","doi":"10.1109/HPEC.2016.7761609","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761609","url":null,"abstract":"A scalable and flexible memory interconnect is a key component for a many-core architecture to take full advantage of the high-bandwidth of multiple memory stacks. In this paper, we discuss both technological and architectural challenges of these processor-to-memory interconnects, and focus on two important issues of many-core memory accesses: traffic hotspots and non-uniform memory access (NUMA). We propose a reconfigurable Silicon photonic memory interconnect based on 2.5D stacking that can direct memory traffic to any memory interface on the processor, thus alleviating the two aforementioned effects in addition to providing high bandwidth. Simulations based on a 16-core 4-memory model show that the proposed architecture can lead to up to 2× STREAM speedup over fixed connections in both hotspot and NUMA scenarios. We also demonstrate the proposed architecture using a four-port Silicon photonic demultiplexer and a 4×4 synthesizable on-chip fabric called OpenSoC. The FPGA-emulated system demonstrates dynamic memory rewiring through wavelength routing, and achieves a reconfiguration time of 5 microseconds.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115784862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"I-vector speaker and language recognition system on Android","authors":"Christian Vázquez-Machado, Pedro Colon-Hernandez, P. Torres-Carrasquillo","doi":"10.1109/HPEC.2016.7761630","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761630","url":null,"abstract":"I-Vector based speaker and language identification provides state of the art performance. However, this comes as a more computationally complex solution, which can often lead to challenges in resource-limited devices, such as phones or tablets. We present the implementation of an I-Vector speaker and language recognition system on the Android platform in the form of a fully functional application that allows speaker enrollment and language/speaker scoring within mobile contexts. We include a detailed account of the challenges to port the system and its dependencies, which were necessary to optimize matrix operations in the I-Vector implementation. The system was benchmarked on a for a Google Nexus 6, showing a speed increase of 61.68% in scoring and 82.63% in enrollment operations with the implemented optimizations. The application was tested in mobile settings on a Nexus 7 tablet with forty participants, showing a rough accuracy of 84%. The optimized platform showed the capacity to perform near real-time recognition within a mobile setting and showcases the viability of I-Vector systems on resource-limited environments.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A quantum macro assembler","authors":"S. Pakin","doi":"10.1109/HPEC.2016.7761637","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761637","url":null,"abstract":"We present a low-level software building block intended to be used to implement higher-level programming models atop quantum annealers such as the D-Wave 2X™. By analogy to a macro assembler for conventional architectures, our quantum macro assembler enables a programmer to express computations symbolically and without regard to the specifics of the underlying hardware. We demonstrate that the quantum macro assembler can be useful in its own right as a programming interface despite providing only a minimal level of hardware abstraction.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121353859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}