{"title":"Computational and memory analysis of Tegra SoCs","authors":"Andrew Milluzzi, A. George, H. Lam","doi":"10.1109/HPEC.2016.7761602","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761602","url":null,"abstract":"Low-power, embedded, GPU System-on-Chip (SoC) devices provide outstanding computational performance, especially for compute-intensive tasks. While clusters of SoCs for High-Performance Embedded Computing (HPEC) are not new, the computational power of these supercomputers has long lacked the efficiency of their more traditional, High-Performance Computing (HPC) counterparts. With the advent of the Tegra K1 and X1, the efficiency debate is significantly more complex. These new devices can provide up to 500 GFLOPS of Float32 performance with a TDP of just 10 Watts. This paper investigates the current state of NVIDIA SoCs, comparing and contrasting their performance and power characteristics to high-end NVIDIA accelerators. In order to perform this analysis, we leverage two metrics, Computational Density (CD) and External Memory Bandwidth (EMB), to provide a first-order estimate and then normalize the results with Realizable Utilization (RU). RU is a measurement of device efficiency, comparing observed benchmarking results to the theoretical CD or EMB. From this analysis, we are able to uncover which computational kernels might show similar or improved performance on an HPEC cluster of NVIDIA Tegra SoCs. Based on our observations, an SoC cluster would be plausible for some power-constrained HPC applications. Furthermore, the observed performance improvement in Tegra devices suggests that a future GPU-SoC cluster could be an option for a wide range of applications.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"476 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An approach to big data inspired by statistical mechanics","authors":"J. Cortese","doi":"10.1109/HPEC.2016.7761643","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761643","url":null,"abstract":"A family of techniques in physics known as statistical mechanics is useful for describing the macroscopic properties of materials composed of a large (Avogadro's # ≈ 1024) number of atoms. This talk applies the same approach to the analysis of big data problems. The initial problem examined is that of classification, specifically binary hypothesis testing, in the big data, high dimensional scenario. The lessons learned from the binary hypothesis testing problem are extended to other signal processing paradigms.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Haidar, Benjamin Brock, S. Tomov, M. Guidry, J. Billings, Daniel Shyles, J. Dongarra
{"title":"Performance analysis and acceleration of explicit integration for large kinetic networks using batched GPU computations","authors":"A. Haidar, Benjamin Brock, S. Tomov, M. Guidry, J. Billings, Daniel Shyles, J. Dongarra","doi":"10.1109/HPEC.2016.7761605","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761605","url":null,"abstract":"We demonstrate the systematic implementation of recently-developed fast explicit kinetic integration algorithms that solve efficiently N coupled ordinary differential equations (subject to initial conditions) on modern GPUs. We take representative test cases (Type Ia supernova explosions) and demonstrate two or more orders of magnitude increase in efficiency for solving such systems (of realistic thermonuclear networks coupled to fluid dynamics). This implies that important coupled, multiphysics problems in various scientific and technical disciplines that were intractable, or could be simulated only with highly schematic kinetic networks, are now computationally feasible. As examples of such applications we present the computational techniques developed for our ongoing deployment of these new methods on modern GPU accelerators. We show that similarly to many other scientific applications, ranging from national security to medical advances, the computation can be split into many independent computational tasks, each of relatively small-size. As the size of each individual task does not provide sufficient parallelism for the underlying hardware, especially for accelerators, these tasks must be computed concurrently as a single routine, that we call batched routine, in order to saturate the hardware with enough work.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"11 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120896392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jordi Ros-Giralt, Alan Y. Commike, R. Lethin, Sourav Maji, M. Veeraraghavan
{"title":"High-performance algorithms and data structures to catch elephant flows","authors":"Jordi Ros-Giralt, Alan Y. Commike, R. Lethin, Sourav Maji, M. Veeraraghavan","doi":"10.1109/HPEC.2016.7761600","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761600","url":null,"abstract":"In high-speed networks, it is important to detect the presence of large flows-also known as elephant flows-because of their adverse effects on delay-sensitive flows. If detected on a timely fashion, network operators can apply active policies such as flow redirection or traffic shaping to ensure the overall quality of service of the network is preserved. Towards this objective, we develop a high-performance data structure and algorithm to address the problem of detecting large flows at very high-speed rates. Our solution leverages the concept of optimal sampling rate under partial information to avoid the need for processing every single packet on the network. With this strategy, we present a prototype of a high-performance network sensor capable of processing traffic rates at 100Gbps and detect the largest flows with high accuracy.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Newton Campbell, Michael J. Laszlo, Sumitra Mukherjee
{"title":"Landmark routing for large graphs in fixed-memory environments","authors":"Newton Campbell, Michael J. Laszlo, Sumitra Mukherjee","doi":"10.1109/HPEC.2016.7761581","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761581","url":null,"abstract":"Point-to-point shortest path distance queries are a core operation in graph analytics. However, preprocessing algorithms that speed up these queries rely on large data structures for reference. In this paper, we discuss the computational challenge introduced by these data structures when using landmark-based preprocessing algorithms on large graphs. We introduce a new heuristic for the A* algorithm that references a data structure of size θ(|L|2 + |V|), where L represents a set of strategically chosen landmark vertices and V the set of vertices in the graph. This heuristic's benefits are permitted by an approach for computing lower bounds based on generalized polygon inequalities. In this approach, each landmark stores the distances between the landmark and vertices within its graph partition. The heuristic is experimentally compared with a previous landmark heuristic in a fixed-memory environment, as an analog to an embedded system. The new heuristic demonstrates a reduction in overall computational time and memory requirements in this environment.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129652238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CUDA implementation of an optimal online Gaussian-Signal-in-Gaussian-Noise detector","authors":"N. Nossenson, Ariel Jaffe","doi":"10.1109/HPEC.2016.7761613","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761613","url":null,"abstract":"We address the computationally demanding task of real time optimal detection of a Gaussian Signal in Gaussian Noise. The mathematical principles of such a detector were formulated in 1965, but a full real-time implementation of these principles was not possible for decades mainly due to technological barriers. We present a CUDA based implementation of such an optimal detector and study its decision making speed (or throughput) as function of target signal duration and signal filter length. We also compare the throughput results to those of a CPU based design. We report on detection rates ranging from 3.5 KHz for a target duration of 10756 samples up to 15.6 KHz for target duration of 92 samples. The CUDA based detector running on 384 parallel cores had a superior throughput comparing to a pure CPU implementation when target duration was longer than 600 samples.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134176029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ToQ.jl: A high-level programming language for D-Wave machines based on Julia","authors":"D. O’Malley, V. Vesselinov","doi":"10.1109/HPEC.2016.7761616","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761616","url":null,"abstract":"Quantum computers are becoming more widely available, so it is important to develop tools that enable people to easily program these computers to solve complex problems. To address this issue, we present the design and two applications of ToQ.jl, a high-level programming language for D-Wave quantum annealing machines. ToQ.jl leverages the metaprogramming facilities in Julia (a high-level, high-performance programming language for technical computing) and uses D-Wave's ToQ programming language as an intermediate representation. This makes it possible for a programmer to leverage all the capabilities of Julia, and the D-Wave machine is used as a co-processor. We demonstrate ToQ.jl via two applications: (1) a pedagogical example based on a map-coloring problem and (2) a linear least squares problem. We also discuss our experience using ToQ.jl with a D-Wave 2X, particularly with respect to a linear least squares problem which is of broad interest to the scientific computing community.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132996232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CUDA implementation of the pagerank pipeline benchmark","authors":"M. Bisson, E. Phillips, M. Fatica","doi":"10.1109/HPEC.2016.7761620","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761620","url":null,"abstract":"This paper presents the details of a CUDA implementation of the PageRank pipeline benchmark [1], a new proposed benchmark aimed to compare and measure the capabilities of big data systems. The reference implementation is only serial at the moment, but our CUDA implementation is parallel. The results indicate that GPU accelerated systems have considerable potential for big data workloads.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133547977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Sanaullah, Saiful A. Mojumder, Kathleen M. Lewis, M. Herbordt
{"title":"GPU-accelerated charge mapping","authors":"A. Sanaullah, Saiful A. Mojumder, Kathleen M. Lewis, M. Herbordt","doi":"10.1109/HPEC.2016.7761599","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761599","url":null,"abstract":"Charge Mapping is critical to electrostatics computations such as performed in Molecular Dynamics simulations. It reduces the complexity of evaluating long-range Coulombic forces by diffusing discrete particle charges onto a regular grid. Acceleration of this stage using GPUs is non-trivial, with the compute and memory intensive nature of the algorithm limiting performance benefits in naive implementations. In this paper, we explore methods for performing efficient charge mapping on GPUs. By utilizing available resources effectively and reducing compute and memory transactions, high throughput can be achieved. Our best case implementation shows > 14 × speed-up over existing GPU codes and > 25 × speed-up over production CPU codes such as NAMD.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"157 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyle L. Labowski, P. Jungwirth, J. Ross, D. Richie
{"title":"Implementing Hilbert transform for Digital Signal Processing on epiphany many-core coprocessor","authors":"Kyle L. Labowski, P. Jungwirth, J. Ross, D. Richie","doi":"10.1109/HPEC.2016.7761638","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761638","url":null,"abstract":"The Adapteva Epiphany MIMD architecture is a scalable 2D array of RISC cores with a fast network-on-chip (NoC) for parallel processing. The work presented here discusses the suitability of the architecture to handle software defined radio (SDR) applications such as Finite Impulse Response (FIR) filters. This paper discusses implementation of the Hilbert filter through using the COPRTHR 2.0 SDK which includes Pthread-like interface for offloading the thread function. We present timing and performance results for our implementation.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130622371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}