2016 IEEE High Performance Extreme Computing Conference (HPEC)最新文献_第2页

The BigDAWG polystore system and architecture BigDAWG多存储系统和架构

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761636

V. Gadepally, Peinan Chen, Jennie Duggan, Aaron J. Elmore, Brandon Haynes, J. Kepner, S. Madden, T. Mattson, M. Stonebraker

{"title":"The BigDAWG polystore system and architecture","authors":"V. Gadepally, Peinan Chen, Jennie Duggan, Aaron J. Elmore, Brandon Haynes, J. Kepner, S. Madden, T. Mattson, M. Stonebraker","doi":"10.1109/HPEC.2016.7761636","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761636","url":null,"abstract":"Organizations are often faced with the challenge of providing data management solutions for large, heterogenous datasets that may have different underlying data and programming models. For example, a medical dataset may have unstructured text, relational data, time series waveforms and imagery. Trying to fit such datasets in a single data management system can have adverse performance and efficiency effects. As a part of the Intel Science and Technology Center on Big Data, we are developing a polystore system designed for such problems. BigDAWG (short for the Big Data Analytics Working Group) is a polystore system designed to work on complex problems that naturally span across different processing or storage engines. BigDAWG provides an architecture that supports diverse database systems working with different data models, support for the competing notions of location transparency and semantic completeness via islands and a middleware that provides a uniform multi-island interface. Initial results from a prototype of the BigDAWG system applied to a medical dataset validate polystore concepts. In this article, we will describe polystore databases, the current BigDAWG architecture and its application on the MIMIC II medical dataset, initial performance results and our future development plans.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131131797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 93

Adding scalability to Internet of Things gateways using parallel computation of edge device data 通过并行计算边缘设备数据，为物联网网关增加可扩展性

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761601

J. Canedo, A. Skjellum

引用次数: 7

A framework to integrate MFiX with Trilinos for high fidelity fluidized bed computations 集成MFiX和Trilinos的框架，用于高保真流化床计算

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761603

Krushnarao Kotteda, A. Chattopadhyay, Vinod Kumar, W. Spotz

引用次数: 7

Efficient implementation of scatter-gather operations for large scale graph analytics 高效实现大规模图形分析的散-聚操作

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761578

Manoj Kumar, M. Serrano, J. Moreira, P. Pattnaik, William P. Horn, J. Jann, Ilie Gabriel Tanase

{"title":"Efficient implementation of scatter-gather operations for large scale graph analytics","authors":"Manoj Kumar, M. Serrano, J. Moreira, P. Pattnaik, William P. Horn, J. Jann, Ilie Gabriel Tanase","doi":"10.1109/HPEC.2016.7761578","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761578","url":null,"abstract":"We developed a methodology to improve the cache behavior and overall performance of sparse linear algebra kernels used in graph analytics. Large scale graph processing typically has low performance because it cannot effectively use processor caches, resulting in high-latency for memory accesses. This is particularly true in a sparse linear algebra formulations of graph algorithms, which use well known kernels such as sparse-matrix vector multiply and sparse-matrix transposition. The proposed methodology partitions the inner loops of linear algebra kernels, and executes the iterations over these partitions in an independently ordered manner. This produces more cache-friendly access patterns, which reduce cache misses and improve performance. We first illustrate the technique through an example and then generalize it to multiple scenarios. Our evaluation shows that execution time of key computational kernels is reduced by 2- to 5-fold, when large graphs are considered. Most of the improvement in execution time comes from a significant reduction in cycles-per-instruction (CPI), even as the path length of the executed code increases.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133934807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Parameter setting for quantum annealers 量子退火炉的参数设置

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761619

K. Pudenz

引用次数: 20

The Open Community Runtime: A runtime system for extreme scale computing 开放社区运行时:一个用于极端规模计算的运行时系统

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761580

T. Mattson, Romain Cledat, Vincent Cavé, Vivek Sarkar, Zoran Budimlic, S. Chatterjee, J. Fryman, Ivan B. Ganev, Rob C. Knauerhase, Min Lee, Benoît Meister, Brian R. Nickerson, Nick Pepperling, B. Seshasayee, Sagnak Tasirlar, J. Teller, Nick Vrvilo

引用次数: 69

Accelerated low-rank updates to tensor decompositions 加速张量分解的低秩更新

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761607

M. Baskaran, M. H. Langston, T. Ramananandro, David Bruns-Smith, Thomas Henretty, J. Ezick, R. Lethin

{"title":"Accelerated low-rank updates to tensor decompositions","authors":"M. Baskaran, M. H. Langston, T. Ramananandro, David Bruns-Smith, Thomas Henretty, J. Ezick, R. Lethin","doi":"10.1109/HPEC.2016.7761607","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761607","url":null,"abstract":"Tensor analysis (through tensor decompositions) is increasingly becoming popular as a powerful technique for enabling comprehensive and complete analysis of real-world data. In many critical modern applications, large-scale tensor data arrives continuously (in streams) or changes dynamically over time. Tensor decompositions over static snapshots of tensor data become prohibitively expensive due to space and computational bottlenecks, and severely limit the use of tensor analysis in applications that require quick response. Effective and rapid streaming (or non-stationary) tensor decompositions are critical for enabling large-scale real-time analysis. We present new algorithms for streaming tensor decompositions that effectively use the low-rank structure of data updates to dynamically and rapidly perform tensor decompositions of continuously evolving data. Our contributions presented here are integral for enabling tensor decompositions to become a viable analysis tool for large-scale time-critical applications. Further, we present our newly-implemented parallelized versions of these algorithms, which will enable more effective deployment of these algorithms in real-world applications. We present the effectiveness of our approach in terms of faster execution of streaming tensor decompositions that directly translate to short response time during analysis.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114796783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

3D DRAM based application specific hardware accelerator for SpMV 基于3D DRAM的SpMV专用硬件加速器

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761633

Fazle Sadi, L. Pileggi, F. Franchetti

{"title":"3D DRAM based application specific hardware accelerator for SpMV","authors":"Fazle Sadi, L. Pileggi, F. Franchetti","doi":"10.1109/HPEC.2016.7761633","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761633","url":null,"abstract":"For numerous scientific applications Sparse Matrix-Vector multiplication (SpMV) is one of the most important kernels. Unfortunately, due to its very low ratio of computation to memory access SpMV is inherently a memory bound problem. On the other hand, the main memory bandwidth of commercial off-the-shelf (COTS) architectures is insufficient for available computation resources on these platforms, well known as the memory wall problem. As a result, COTS architectures are unsuitable for SpMV. Furthermore, SpMV requires random access into a memory space which is far too big for cache. Hence, it becomes difficult to utilize the main memory bandwidth which is already scarce. We propose an algorithm for large SpMV problems which is specially optimized to fully exploit the underlying micro-architecture and overall system capabilities. This algorithm is implemented in two steps. The key feature of the first step is that it converts all the main memory random access into streaming access. This reduces the overall data transfer volume significantly and ensures full utilization of the memory bandwidth. On top of that, we propose a meta-data compression technique, namely Variable Length Delta Index (VLDI), to decrease the data transfer volume even further. VLDI is particularly effective for sparse matrices where meta-data to payload ratio is high, e.g. sparse bit matrices.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129412441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

LU, QR, and Cholesky factorizations: Programming model, performance analysis and optimization techniques for the Intel Knights Landing Xeon Phi LU, QR，和Cholesky分解:编程模型，性能分析和优化技术为英特尔骑士登陆至强Phi

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761591

A. Haidar, S. Tomov, Konstantin Arturov, M. Guney, S. Story, J. Dongarra

{"title":"LU, QR, and Cholesky factorizations: Programming model, performance analysis and optimization techniques for the Intel Knights Landing Xeon Phi","authors":"A. Haidar, S. Tomov, Konstantin Arturov, M. Guney, S. Story, J. Dongarra","doi":"10.1109/HPEC.2016.7761591","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761591","url":null,"abstract":"A wide variety of heterogeneous compute resources, ranging from multicore CPUs to GPUs and coprocessors, are available to modern computers, making it challenging to design unified numerical libraries that efficiently and productively use all these varied resources. For example, in order to efficiently use Intel's Knights Landing (KNL) processor, the next-generation of Xeon Phi architectures, one must design and schedule an application in multiple degrees of parallelism and task grain sizes in order to obtain efficient performance. We propose a productive and portable programming model that allows us to write a serial-looking code, which, however, achieves parallelism and scalability by using a lightweight runtime environment to manage the resource-specific workload, and to control the dataflow and the parallel execution. This is done through multiple techniques ranging from multi-level data partitioning to adaptive task grain sizes, and dynamic task scheduling. In addition, our task abstractions enable unified algorithmic development across all the heterogeneous resources. Finally, we outline the strengths and the effectiveness of this approach - especially in regards to hardware trends and ease of programming high-performance numerical software that current applications need - in order to motivate current work and future directions for the next generation of parallel programming models for high-performance linear algebra libraries on heterogeneous systems.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus 基于PCIe总线的GPU加速集群系统优化数据传输的设计空间探索

2016 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2016-09-01 DOI: 10.1109/HPEC.2016.7761614

J. Bhimani, M. Leeser, N. Mi

{"title":"Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus","authors":"J. Bhimani, M. Leeser, N. Mi","doi":"10.1109/HPEC.2016.7761614","DOIUrl":"https://doi.org/10.1109/HPEC.2016.7761614","url":null,"abstract":"Use of accelerators such as GPUs is increasing, but efficient use of GPUs requires making good design choices. Such design choices include type of memory allocation and overlapping concurrency of data transfer with parallel computation. Performance varies with the application, hardware version such as generation of GPU, and software version including programming language drivers. This large number of design decisions makes it nearly impossible to obtain the optimal performance point by directly porting any application. This emphasizes the need for high level design decision guidelines for GPU accelerated cluster systems, applicable to a broad class of applications rather than any specific application. This paper proposes novel design guidelines for GPU accelerated cluster systems, to optimize the data transfer from host (CPU) to device (GPU) using the PCIe bus. In particular, we consider design choices offered by NVIDIA GPUs. Our main contribution is to build design guidelines that are applicable to a broad class of applications. We design 27 different versions of the same micro benchmark, where the design choices made by each version is unique. We observe that a speedup of 2.6x can be obtained just by making good design choices.","PeriodicalId":308129,"journal":{"name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114453797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4