Proceedings of the 47th International Conference on Parallel Processing最新文献_第5页

HUS-Graph: I/O-Efficient Out-of-Core Graph Processing with Hybrid Update Strategy us -Graph:基于混合更新策略的I/ o高效核外图处理

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225108

Xianghao Xu, F. Wang, Hong Jiang, Yongli Cheng, D. Feng, Yongxuan Zhang

{"title":"HUS-Graph: I/O-Efficient Out-of-Core Graph Processing with Hybrid Update Strategy","authors":"Xianghao Xu, F. Wang, Hong Jiang, Yongli Cheng, D. Feng, Yongxuan Zhang","doi":"10.1145/3225058.3225108","DOIUrl":"https://doi.org/10.1145/3225058.3225108","url":null,"abstract":"In recent years, a number of out-of-core graph processing systems have been proposed to process graphs with billions of edges on just one commodity computer, due to their high cost efficiency. To obtain the better performance, these systems adopt a full I/O model that accesses all edges during the computation to avoid the ineffectiveness of random I/Os. Although this model ensures good I/O access locality, it loads a large number of useless edges when running graph algorithms that only require a small portion of edges in each iteration. A natural method to solve this problem is the on-demand I/O model that only accesses the active edges. However, this method only works well for the graph algorithms with very few active edges, since the I/O cost will grow rapidly as the number of active edges increases due to larger amount of random I/Os. In this paper, we present HUS-Graph, an efficient out-of-core graph processing system to address the above I/O issues and achieve a good balance between I/O amount and I/O access locality. HUS-Graph first adopts a hybrid update strategy including two update models, Row-oriented Push (ROP) and Column-oriented Pull (COP). It can adaptively select the optimal update model for the graph algorithms that have different computation and I/O features, based on an I/O-based performance prediction method. Furthermore, HUS-Graph proposes a dual-block representation to organize graph data, which ensures good access locality. Extensive experimental results show that HUS-Graph outperforms existing out-of-core systems by 1.4x-23.1x.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114549980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

NumLock

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225141

S. Kalikar, R. Nasre

{"title":"NumLock","authors":"S. Kalikar, R. Nasre","doi":"10.1145/3225058.3225141","DOIUrl":"https://doi.org/10.1145/3225058.3225141","url":null,"abstract":"We study multi-granularity locking in hierarchies. Existing popular mechanisms for multi-granularity locking work on two extremes: fine-grained locking which maximizes concurrency, and coarsegrained locking which minimizes the locking cost. Between the two extremes, there exist several pareto-optimal options which provide a trade-off between the concurrency cost and the locking cost. These options are captured under multi-granularity locking (MGL) protocol, but there exists no methodical way to choose a good MGL option. In this work, we present a locking technique, NumLock, which chooses optimal locking combination to serve MGL requests. NumLock works in two phases: first, it generates few pareto-optimal MGL options and second, it quickly analyzes these options to report the optimal one. We propose a greedy algorithm to generate a subset of the pareto-optimal options. We further improve the concurrency by abstracting the non-planar hierarchy as logical planar sub-hierarchies using multiple intervals. Our study reveals that the lock manager must explore various MGL options for achieving the best parallel performance, and that the extreme options often used in practice are suboptimal. We validate our claim quantitatively using an XML database as well as STMBench7, and show that the intermediate MGL options perform better compared to the existing state-of-the-art methods. In particular, NumLock achieves 65% reduction in execution time for the XML database, and 25% throughput improvement on STMBench7.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115439487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Modeling Application Resilience in Large-scale Parallel Execution 大规模并行执行中的应用弹性建模

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225119

Kai Wu, Wenqian Dong, Qiang Guan, Nathan Debardeleben, Dong Li

{"title":"Modeling Application Resilience in Large-scale Parallel Execution","authors":"Kai Wu, Wenqian Dong, Qiang Guan, Nathan Debardeleben, Dong Li","doi":"10.1145/3225058.3225119","DOIUrl":"https://doi.org/10.1145/3225058.3225119","url":null,"abstract":"Understanding how the application is resilient to hardware and software errors is critical to high-performance computing. To evaluate application resilience, the application level fault injection is the most common method. However, the application level fault injection can be very expensive when running the application in parallel in large scales due to the high requirement for hardware resource during fault injection. In this paper, we introduce a new methodology to evaluate the resilience of the application running in large scales. Instead of injecting errors into the application in large-scale execution, we inject errors into the application in small-scale execution and serial execution to model and predict the fault injection result for the application running in large scales. Our models are based on a series of empirical observations. Those observations characterize error occurrences and propagation across MPI processes in small-scale execution (including serial execution) and large-scale one. Our models achieve high prediction accuracy. Evaluating with four NAS parallel benchmarks and two proxy scientific applications, we demonstrate that using the fault injection result to predict for 64 MPI processes, the average prediction error is 8%. While using the fault injection result to make the same prediction for eight MPI processes, the average prediction error decreases to 7%.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129754618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Index Shard Replication Strategies for Improving Resource Utilization in Large Scale Search Engines 提高大规模搜索引擎资源利用率的索引分片复制策略

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225102

Yusen Li, Xueyan Tang, Wentong Cai, Jiancong Tong, Xiaoguang Liu, Gang Wang, Chuansong Gao, Xuan Cao, Guanhui Geng, Minghui Li

{"title":"Index Shard Replication Strategies for Improving Resource Utilization in Large Scale Search Engines","authors":"Yusen Li, Xueyan Tang, Wentong Cai, Jiancong Tong, Xiaoguang Liu, Gang Wang, Chuansong Gao, Xuan Cao, Guanhui Geng, Minghui Li","doi":"10.1145/3225058.3225102","DOIUrl":"https://doi.org/10.1145/3225058.3225102","url":null,"abstract":"With the rapid growth of the Web scale, large scale search engines have to set up a huge number of machines to place the index files of the Web contents. The index files are normally divided into smaller index shards which are often replicated so that queries can be processed in parallel. We observe that the index shard replication strategy could have a significant impact on the resource utilization of machines. In this paper, we investigate the index shard replication problem with the goal of improving the resource utilization of machines in search engine datacenters. We formulate the problem as a variant of the Multi-Dimensional Vector Bin Packing Problem and propose several strategies to approximate the optimal solution. The proposed strategies are evaluated by extensive experiments using data from real commercial search engines. The results demonstrate the effectiveness of the proposed strategies. Our work also yields many insights about the impact of different input properties on the performance and the key factors that each strategy is sensitive to. We believe that this paper will provide valuable guidance to the choice of the index shard replication strategy in practice.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

FULT FULT

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225115

Hoang-Vu Dang, M. Snir

引用次数: 0

KeyBin2

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225149

Xinyu Chen, Jeremy Benson, Matt Peterson, M. Taufer, Trilce Estrada

引用次数: 1

Power Efficient High Performance Packet I/O 高效高效的包I/O

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225129

Xuesong Li, Wenxue Cheng, Tong Zhang, Jingmin Xie, Fengyuan Ren, Bailong Yang

{"title":"Power Efficient High Performance Packet I/O","authors":"Xuesong Li, Wenxue Cheng, Tong Zhang, Jingmin Xie, Fengyuan Ren, Bailong Yang","doi":"10.1145/3225058.3225129","DOIUrl":"https://doi.org/10.1145/3225058.3225129","url":null,"abstract":"Recently, high performance packet I/O frameworks are expected an extensive application for their ability to process packets from 10Gbps or higher speed links. To achieve high throughput and low latency, high performance packet I/O frameworks usually employ busy polling technique. As busy polling will burn all CPU cycles even if there's no packet to process, these frameworks are quite power inefficient. Meanwhile, exploiting power management techniques such as DVFS and LPI in high performance packet I/O frameworks is challenging, because neither the OS nor the frameworks can provide information (e.g., the actual CPU utilization, available idle period, or the target frequency) required by power management techniques. In this paper, we establish an analytical model that can formulate the packet processing flow of high performance packet I/O to help address the above challenges. From the analytical model, we can deduce the actual CPU utilization and average idle period in different traffic load, and gain the insight to choose CPU frequency that can appropriately balance the power consumption and packet latency. Then, we propose two simple but effective approaches to conduct power conservation for high performance packet I/O: one with the aid of traffic information and the other without. Experiments with Intel DPDK show that both approaches can achieve significant power reduction (35.90% and 34.43% on average respectively) while incurring < 1 μs of latency increase.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Duchy 公国

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225067

Xuchao Xie, Tianye Yang, Qiong Li, Dengping Wei, Liquan Xiao

引用次数: 13

A Communication-Efficient Causal Broadcast Protocol 一种通信高效的因果广播协议

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225121

J. Araujo, L. Arantes, E. P. Duarte, L. A. Rodrigues, Pierre Sens

引用次数: 2

Bandwidth Reduced Parallel SpMV on the SW26010 Many-Core Platform SW26010多核平台上带宽降低的并行SpMV

Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225074

Qiao Sun, Changyou Zhang, Changmao Wu, Jiajia Zhang, Leisheng Li

{"title":"Bandwidth Reduced Parallel SpMV on the SW26010 Many-Core Platform","authors":"Qiao Sun, Changyou Zhang, Changmao Wu, Jiajia Zhang, Leisheng Li","doi":"10.1145/3225058.3225074","DOIUrl":"https://doi.org/10.1145/3225058.3225074","url":null,"abstract":"SpMV (Sparse Matrix-Vector multiplication), in its simplest form y = Ax, multiplies a sparse matrix with a dense vector and is a widely used computing primitive in the domain of HPC. On the newly SW26010 many-core platform, we propose a highly efficient CSR (Compressed Storage Row) based implementation of parallel SpMV, referred to as SWCSR-SpMV in the sequel. SpMV in the CSR format can be trivially parallelized but its performance is majorly impeded by memory access efficiency, and therefore to leverage high-throughput memory access mechanism while avoiding redundant bandwidth usage becomes the major goal of designing high performance SpMV on the target platform. The original problem is sequentially partitioned into row-slices, each of which can reside in the fast scratchpad memory, so that the loaded x'es can be reused; meanwhile, a dynamic look-ahead scheme is applied to avoid redundant memory access; we split the many-core mesh into smaller communication scope to facilitate the sharing of the common data across the working threads via the high speed on-mesh data bus. Beyond the above, to leverage massive parallelism balanced workload is ensured by both static and dynamic means. Performance evaluation is done on a benchmark of 36 frequently used sparse matrices in the fields of graph computing, data mining, computational fluid dynamics, etc.. While the performance upper-bound is defined by the ratio between the minimal data access volume required against the practically optimal bandwidth, ignoring the computing overhead, SWCSR-SpMV can achieve an efficiency of nearly 87%, maintaining over 75% for 1/3 of the testing matrices. SWCSR-SpMV is further applied in a PETSc based application, a 1.75x-2.6x speedup is sustained in a multi-process environment on the Sunway TaiHuLight supercomputer.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131865385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8