Proceedings of the 47th International Conference on Parallel Processing最新文献

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Toward Performant and Energy-efficient Queries in Three-tier Wireless Sensor Networks 面向三层无线传感器网络的性能和节能查询
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225073
Jiayao Wang, Abdullah Al-Mamun, Tonglin Li, Linhua Jiang, Dongfang Zhao
{"title":"Toward Performant and Energy-efficient Queries in Three-tier Wireless Sensor Networks","authors":"Jiayao Wang, Abdullah Al-Mamun, Tonglin Li, Linhua Jiang, Dongfang Zhao","doi":"10.1145/3225058.3225073","DOIUrl":"https://doi.org/10.1145/3225058.3225073","url":null,"abstract":"In a wireless sensor network (WSN) where nodes are mostly battery-powered, queries' energy consumption and response time are two of the most important metrics as they represent the network's sustainability and performance, respectively. Conventional techniques used to focus only one of the two metrics and did not attempt to optimize both in a coordinated manner. This work aims to achieve both high sustainability and high performance of WSN queries at the same time. To that end, a new mechanism is proposed to construct the topology of a three-tier WSN. The proposed mechanism eliminates routing tables and employs a novel and efficient addressing scheme inspired by the Chinese Remainder Theorem (CRT). The CRT-based topology allows for query parallelism, an unprecedented feature in WSNs. On top of the new topology encoded by CRT, a new protocol is designed to parallelly preprocess collected data on sensor nodes by effectively aggregating and deduplicating data in a neighborhood cluster. Moreover, a new algorithm is devised to allow the queries and results to be transmitted through low-power and fault-tolerant paths using recursive elections over a subset of the entire power range. With all these new techniques combined, the proposed system outperforms the state-of-the-art from various perspectives: (i) the query response is improved by up to 53%; (ii) the energy consumption is reduced by up to 70%; and (iii) the reliability is increased by up to 39%.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Accelerating FM-index Search for Genomic Data Processing 加速基因组数据处理中的fm索引搜索
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225134
Yuanrong Wang, Xueqi Li, Dawei Zang, Guangming Tan, Ninghui Sun
{"title":"Accelerating FM-index Search for Genomic Data Processing","authors":"Yuanrong Wang, Xueqi Li, Dawei Zang, Guangming Tan, Ninghui Sun","doi":"10.1145/3225058.3225134","DOIUrl":"https://doi.org/10.1145/3225058.3225134","url":null,"abstract":"The deluge of genomics data is incurring prohibitively high computational costs. As an important building block for genomic data processing algorithms, FM-index search occupies most of execution time in sequence alignment. Due to massive random streaming memory references relative to only small amount of computations, FM-index search algorithm exhibits extremely low efficiency on conventional architectures. This paper proposes Niubility, an accelerator for FM-index search in genomic sequence alignment. Based on our algorithm-architecture co-design analysis, we found that conventional architectures exploit low memory-level parallelism so that the available memory bandwidth cannot be fully utilized. Niubility accelerator customizes bit-wise operations and exploit data-level parallelism, that produces maximal concurrent memory accesses to saturate memory bandwidth. We implement an accelerator ASIC in a ST 28nm process that achieves up to 990x speedup over the state-of-the-art software.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125144481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection 利用动态线路保护提高gpu的一级缓存效率
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225104
Xian Zhu, R. Wernsman, Joseph Zambreno
{"title":"Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection","authors":"Xian Zhu, R. Wernsman, Joseph Zambreno","doi":"10.1145/3225058.3225104","DOIUrl":"https://doi.org/10.1145/3225058.3225104","url":null,"abstract":"A modern Graphics Processing Unit (GPU) utilizes L1 Data (L1D) caches to reduce memory bandwidth requirements and latencies. However, the L1D cache can easily be overwhelmed by many memory requests from GPU function units, which can bottleneck GPU performance. It has been shown that the performance of L1D caches is greatly reduced for many GPU applications as a large amount of L1D cache lines are replaced before they are re-referenced. By examining the cache access patterns of these applications, we observe L1D caches with low associativity have difficulty capturing data locality for GPU applications with diverse reuse patterns. These patterns result in frequent line replacements and low data re-usage. To improve the efficiency of L1D caches, we design a Dynamic Line Protection scheme (DLP) that can both preserve valuable cache lines and increase cache line utilization. DLP collects data reuse information from the L1D cache. This information is used to predict protection distances for each memory instruction at runtime, which helps maintain a balance between exploitation of data locality and over-protection of cache lines with long reuse distances. When all cache lines are protected in a set, redundant cache misses are bypassed to reduce the contention for the set. The evaluation result shows that our proposed solution improves cache hits while reducing cache traffic for cache-insufficient applications, achieving up to 137% and an average of 43% IPC improvement over the baseline.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114293053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Energy-Efficient Speculative Execution using Advanced Reservation for Heterogeneous Clusters 基于高级预留的异构集群节能推测执行
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225084
Amelie Chi Zhou, Tien D. Phan, Shadi Ibrahim, Bingsheng He
{"title":"Energy-Efficient Speculative Execution using Advanced Reservation for Heterogeneous Clusters","authors":"Amelie Chi Zhou, Tien D. Phan, Shadi Ibrahim, Bingsheng He","doi":"10.1145/3225058.3225084","DOIUrl":"https://doi.org/10.1145/3225058.3225084","url":null,"abstract":"Many Big Data processing applications nowadays run on large-scale multi-tenant clusters. Due to hardware heterogeneity and resource contentions, straggler problem has become the norm rather than the exception in such clusters. To handle the straggler problem, speculative execution has emerged as one of the most widely used straggler mitigation techniques. Although a number of speculative execution mechanisms have been proposed, as we have observed from real-world traces, the questions of \"when\" and \"where\" to launch speculative copies have not been fully discussed and hence cause inefficiencies on the performance and energy of Big Data applications. In this paper, we propose a performance model and an energy consumption model to reveal the performance and energy variations with different speculative execution solutions. We further propose a window-based dynamic resource reservation and a heterogeneity-aware copy allocation technique to answer the \"when\" and \"where\" questions for speculative executions. Evaluations using real-world traces show that our proposed technique can improve the performance of Big Data applications by up to 30% and reduce the overall energy consumption by up to 34%.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128776865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Disk Failure Prediction in Data Centers via Online Learning 基于在线学习的数据中心磁盘故障预测
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225106
Jiang Xiao, Zhuang Xiong, Song Wu, Yusheng Yi, Hai Jin, Kan Hu
{"title":"Disk Failure Prediction in Data Centers via Online Learning","authors":"Jiang Xiao, Zhuang Xiong, Song Wu, Yusheng Yi, Hai Jin, Kan Hu","doi":"10.1145/3225058.3225106","DOIUrl":"https://doi.org/10.1145/3225058.3225106","url":null,"abstract":"Disk failure has become a major concern with the rapid expansion of storage systems in data centers. Based on SMART (Self-Monitoring, Analysis and Reporting Technology) attributes, many researchers derive disk failure prediction models using machine learning techniques. Despite the significant developments, the majority of works rely on offline training and thereby hinder their adaption to the continuous update of forthcoming data, suffering from the 'model aging' problem. We are therefore motivated to uncover the root cause -- the dynamic SMART distribution for 'model aging', aiming to resolve the performance degradation as to pave a comprehensive study in practice. In this paper, we introduce a novel disk failure prediction model using Online Random Forests (ORFs). Our ORF-based model can automatically evolve with sequential arrival of data on-the-fly and thus is highly adaptive to the variance of SMART distribution over time. Moreover, it has favourable advantage against the offline counterparts in terms of superior prediction performance. Experiments on real-world datasets show that our ORF model converges rapidly to the offline random forests and achieves stable failure detection rates of 93-99% with low false alarm rates. Furthermore, we demonstrate the ability of our approach on maintaining stable prediction performance for the long-term usage in data centers.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126276047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability 利用硬件事务内存中的冗余来提高缓存可靠性
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225093
Zhichao Yan, Hong Jiang, W. Srisa-an, S. Seth, Yujuan Tan
{"title":"Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability","authors":"Zhichao Yan, Hong Jiang, W. Srisa-an, S. Seth, Yujuan Tan","doi":"10.1145/3225058.3225093","DOIUrl":"https://doi.org/10.1145/3225058.3225093","url":null,"abstract":"Soft error is a type of transient errors that occur due in part to reductions in capacitance and operating voltages in modern electronic components. Recently, the problem of soft errors has become more prevalent due to several design factors, including aggressive device scaling and newer energy-efficient designs, thus significantly threatening the reliability of computer systems. Since the occurrence of soft errors is non-deterministic, detecting them and recovering from them can be quite challenging. A common way to detect soft errors is to execute two identical program instances and then compare their results. Although this approach is effective, it is not efficient as both non-trivial computation and memory resources must be invested to support such redundant executions. The introduction of hardware transactional memory (HTM) in modern chip multiprocessors (CMPs) provides an opportunity to leverage its redundant information to address the emerging reliability concerns including soft errors. In this work, we propose and implement a reliability-enhanced HTM system, called RE-HTM, which leverages redundancy to detect soft errors occurring in the L1 data cache and then recover from them. We then empirically evaluate RE-HTM and the results indicate that RE-HTM is more effective than the existing approach of running two redundant execution instances while incurring lower runtime overhead on protecting L1 data cache from soft errors.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115870195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Constructing Dynamic Policies for Paging Mode Selection 构建分页模式选择的动态策略
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225082
Jason Hiebel, Laura E. Brown, Zhenlin Wang
{"title":"Constructing Dynamic Policies for Paging Mode Selection","authors":"Jason Hiebel, Laura E. Brown, Zhenlin Wang","doi":"10.1145/3225058.3225082","DOIUrl":"https://doi.org/10.1145/3225058.3225082","url":null,"abstract":"Virtualization technology is a key component for data center management which allows for multiple users and applications to share a single, physical machine. Modern virtual machine monitors utilize both software and hardware-assisted paging for memory virtualization, however neither paging mode is always preferable. Previous studies have shown that dynamic selection, which at runtime selects paging modes according to relevant performance metrics, can be effective in tailoring memory virtualization to program workload. However, these approaches require low-level manual analysis, or depend on prior knowledge of workload characteristics and phasing. We map the problem of dynamic paging mode selection to the contextual bandit, a model for sequential decision making in environments with limited feedback. Utilizing random profiling, which executes a workload while regularly selecting paging modes at random, we construct a paging mode selection policy that dynamically optimizes workload performance given page fault and translation lookaside buffer miss counts. Our approach yields an effective policy, DSP-OFFSET, for the dynamic paging mode selection problem. When trained and evaluated on subsets of the SPEC CPU2006 benchmark suite, DSP-OFFSET achieves speedups up to 44% compared to static paging mode selections, which is equivalent to the performance of the state-of-the-art ASP-SVM model. In addition, DSP-OFFSET requires at most a tenth of the profiling time of ASP-SVM (2.5 hours compared to over 24 hours) to achieve equivalent performance.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"143 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132502542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Performance Model to Execute Workflows on High-Bandwidth-Memory Architectures 在高带宽内存架构上执行工作流的性能模型
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225110
A. Benoit, Swann Perarnau, L. Pottier, Y. Robert
{"title":"A Performance Model to Execute Workflows on High-Bandwidth-Memory Architectures","authors":"A. Benoit, Swann Perarnau, L. Pottier, Y. Robert","doi":"10.1145/3225058.3225110","DOIUrl":"https://doi.org/10.1145/3225058.3225110","url":null,"abstract":"This work presents a realistic performance model to execute scientific workflows on high-bandwidth-memory architectures such as the Intel Knights Landing. We provide a detailed analysis of the execution time on such platforms, taking into account transfers from both fast and slow memory and their overlap with computations. We discuss several scheduling and mapping strategies: not only tasks must be assigned to computing resources, but also one has to decide which fraction of input and output data will reside in fast memory and which will have to stay in slow memory. We use extensive simulations to assess the impact of the mapping strategies on performance. We also conduct experiments for a simple 1D Gauss-Seidel kernel, which assess the accuracy of the model and further demonstrate the importance of a tuned memory management. Our model and results lay the foundations for further studies and experiments on dual-memory systems.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131582107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Cross-Rack-Aware Updates in Erasure-Coded Data Centers 擦除编码数据中心的跨机架感知更新
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225065
Zhirong Shen, P. Lee
{"title":"Cross-Rack-Aware Updates in Erasure-Coded Data Centers","authors":"Zhirong Shen, P. Lee","doi":"10.1145/3225058.3225065","DOIUrl":"https://doi.org/10.1145/3225058.3225065","url":null,"abstract":"The update performance in erasure-coded data centers is often bottlenecked by the constrained cross-rack bandwidth. We propose CAU, a cross-rack-aware update mechanism that aims to mitigate the cross-rack update traffic in erasure-coded data centers. CAU builds on three design elements: (i) selective parity updates, which select the appropriate parity update approach based on the update pattern and the data layout to reduce the cross-rack update traffic; (ii) data grouping, which relocates and groups updated data chunks in the same rack to further reduce the cross-rack update traffic; and (iii) interim replication, which stores a temporary replica for each newly updated data chunk. We evaluate CAU via trace-driven analysis, local cluster experiments, and Amazon EC2 experiments. We show that CAU enhances state-of-the-arts by mitigating the cross-rack update traffic as well as maintaining high update performance in both local cluster and geo-distributed environments.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114428772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
NumaMMA: NUMA MeMory Analyzer NumaMMA: NUMA内存分析器
Proceedings of the 47th International Conference on Parallel Processing Pub Date : 2018-08-13 DOI: 10.1145/3225058.3225094
François Trahay, Manuel Selva, L. Morel, K. Marquet
{"title":"NumaMMA: NUMA MeMory Analyzer","authors":"François Trahay, Manuel Selva, L. Morel, K. Marquet","doi":"10.1145/3225058.3225094","DOIUrl":"https://doi.org/10.1145/3225058.3225094","url":null,"abstract":"Non Uniform Memory Access (NUMA) architectures are nowadays common for running High-Performance Computing (HPC) applications. In such architectures, several distinct physical memories are assembled to create a single shared memory. Nevertheless, because there are several physical memories, access times to these memories are not uniform depending on the location of the core performing the memory request and on the location of the target memory. Hence, threads and data placement are crucial to efficiently exploit such architectures. To help in taking decision about this placement, profiling tools are needed. In this work, we propose NUMA MeMory Analyzer (NumaMMA), a new profiling tool for understanding the memory access patterns of HPC applications. NumaMMA combines efficient collection of memory traces using hardware mechanisms with original visualization means allowing to see how memory access patterns evolve over time. The information reported by NumaMMA allows to understand the nature of these access patterns inside each object allocated by the application. We show how NumaMMA can help understanding the memory patterns of several HPC applications in order to optimize them and get speedups up to 28% over the standard non optimized version.","PeriodicalId":307809,"journal":{"name":"Proceedings of the 47th International Conference on Parallel Processing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115064564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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