{"title":"Reliable design with multiple clock domains","authors":"Ed Czeck, Ravi Nanavati, Joe Stoy","doi":"10.1109/MEMCOD.2006.1695917","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695917","url":null,"abstract":"We present a set of guiding principles for the management of multiple clocks domains in the design of a high-level hardware description language. Our motivation of the requirements is based on typical design problems; the solutions are based on common engineering practices and appropriate language abstractions. We include examples, and conclude with some comments based on a design experience","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128188235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Doucet, Ingolf Krüger, Rajesh K. Gupta, R. Shyamasundar
{"title":"Compositional interaction specifications for SystemC","authors":"F. Doucet, Ingolf Krüger, Rajesh K. Gupta, R. Shyamasundar","doi":"10.1109/MEMCOD.2006.1695930","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695930","url":null,"abstract":"SystemC is being widely used for system-level modeling of system-on-chip. When designing this class of system, one of the main challenges is to guarantee the correctness of the implementation. This can be especially difficult for designs that are composed of concurrent components with lot of interactions. Most designers use a component-based design approach, where one has an informal idea of how the design should behave, define component specifications, implement and assemble the components into a program, and then check for correctness by simulating the design with a number of testbenches. With this methodology, bugs often go undetected because when using simulation, it is very difficult to test for all possible interactions. To overcome this limitation, our goal is to establish a specification and verification methodology for SystemC. To address the scalability issue, which is a serious limiting factor in state-based verification approaches, we use the concepts of behavioral types; allowing us to effectively infer system properties from properties of its components. In this paper, we answer the following questions: (1) what is a behavioral type? (2) how are behavioral type defined? and (3) how to use the behavioral types in a compositional verification methodology","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scalable program analysis using Boolean satisfiability","authors":"A. Aiken","doi":"10.1109/MEMCOD.2006.1695908","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695908","url":null,"abstract":"Summary form only given. Static program analysis suffers from a fundamental trade-off between precision and scalability, and the analyses that scale to the largest programs are generally not the most precise methods known. This talk describes how recent advances in algorithms for solving instances of Boolean satisfiability (SAT) can be exploited to relax this trade-off, resulting in analyses that are both more precise and more scalable than existing techniques, as well as how these improved capabilities might be used in verification of properties of large systems","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133166591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Component-based hardware/software co-verification","authors":"Fei Xie, Guowu Yang, Xiaoyu Song","doi":"10.1109/MEMCOD.2006.1695897","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695897","url":null,"abstract":"We present a novel component-based approach to hardware/software co-verification of embedded systems using model checking. Due to their diverse applications and often strict physical constraints, embedded systems are increasingly component-based and include only the necessary components for their missions. In our approach, a component model for embedded systems which unifies the concepts of hardware IPs (i.e., hardware components) and software components is defined. Hardware and software components are verified as they are developed bottom-up. Whole systems are co-verified as they are developed top-down. Interactions of bottom-up and top-down verification are exploited to reduce verification complexity by facilitating compositional reasoning and verification reuse. Case studies on a suite of networked sensors have shown that our approach facilitates major verification reuse and leads to order-of-magnitude reduction on verification complexity","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The SystemJ approach to system-level design","authors":"F. Gruian, P. Roop, Z. Salcic, Ivan Radojevic","doi":"10.1109/MEMCOD.2006.1695918","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695918","url":null,"abstract":"In this paper, we propose a new system-level design language, called SystemJ. It extends Java with synchronous reactive features present in Esterel and asynchronous constructs suitable for modelling globally asynchronous locally synchronous systems. The strength of SystemJ comes from its ability to offer the data processing and encapsulation elegance of Java, Esterel-like reactivity and synchrony, and the asynchronous de-coupling of CSP all within the Java framework. Using standard Java environments, for specification and modelling, or specialised reactive embedded processors, for high performance implementation, the SystemJ design flow is extremely versatile. With the increasing attention that Java gets in embedded systems, SystemJ comes to address data and control, software and hardware, modelling and implementation in a unified manner","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114170100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Formal methods for checking realizability of coalitions in 3-party systems","authors":"A. Banerjee, P. Dasgupta, P. Chakrabarti","doi":"10.1109/MEMCOD.2006.1695927","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695927","url":null,"abstract":"The main contributions of this paper are as follows: We revisit the concept of multiplayer coalition games in the context of a 3-party system. We analyze the coalition realizability problem for different degrees of observability of the module and the controller. We show that the realizability problem can be expressed as an instance of quantified Boolean formulas (QBF), by using appropriate quantifications on the variables of the environment, the module and the controller. We then use recent QBF solvers to verify","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122724303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Panel: Nano-computing - do we need new formal approaches ?","authors":"M. Hsiao, S. Shukla, M. Gokhale, A. Lebeck","doi":"10.1109/MEMCOD.2006.1695906","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695906","url":null,"abstract":"With current CMOS technologies reaching beyond 65 nanometers mark, and the highlights of computing fabrics such as molecular, DNA guided assemblies, quantum comput- ing, carbon nanotube based transistors etc. are bringing the focus onto nanotechnology.The term nano-computing now implies computing with alternative emerging nano-scale technologies as well as with large scale parallelism afforded by the shrinking silicon technologies, with the added burden of rampant defects and faults. The optimization factors and assumptions we made so far in hardware designs become no longer valid for such computing fabrics. The parallelism heretofore unavailable can now be applied, and help us realize newer ways of designing softwares and algorithms. The question therefore to ask is: do we need drastic new approaches to design hardware and software? This panel comprising of experts from formal methods, reliability, spatial computing, hardware/software design will discuss this question from individual perspectives in an attempt to come up with a cogent set of questions researchers need to answer.","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125791805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Games for formal design and verification of reactive systems","authors":"R. Alur","doi":"10.1109/MEMCOD.2006.1695893","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695893","url":null,"abstract":"Summary form only given. With recent advances in algorithms for state-space traversal and in techniques for automatic abstraction of source code, model checking has emerged as a key tool for analyzing and debugging software systems. This talk discusses the role of games in modeling and analysis of software systems. Games are useful in modeling open systems where the distinction among the choices controlled by different components is made explicit. We first describe the model checker Mocha that supports a game-based temporal logic for writing requirements, and its applications to analysis of multi-party security protocols. Then, we describe how to automatically extract dynamic interfaces for Java classes using predicate abstraction for extracting a Boolean model from a class file, and learning algorithms for constructing the most general strategy for invoking the methods of the model. We discuss an implementation in the tool JIST - Java Interface Synthesis Tool and demonstrate that the tool can construct interfaces, accurately and efficiently, for sample Java2SDK library' classes","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127346627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Keynote Talk I","authors":"S. Shukla","doi":"10.1109/memcod.2006.1695892","DOIUrl":"https://doi.org/10.1109/memcod.2006.1695892","url":null,"abstract":"","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122905976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings. Fourth ACM & IEEE International Conference on Formal Methods and Models for Co-Design. (MEMOCODE'06) (IEEE Cat. No. 06EX1398)","authors":"","doi":"10.1109/MEMCOD.2006.1695887","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695887","url":null,"abstract":"The following topics are dealt with: formal methods; model checking; rule-based hardware design; hardware verification; transaction level modeling; programming models; SoC-implemented architectures; time and clocks; and scheduling.","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114473929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}