Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.最新文献

{"title":"Efficient code generation from synchronous programs","authors":"K. Schneider, J. Brandt, Eric Vecchié","doi":"10.1109/MEMCOD.2006.1695922","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695922","url":null,"abstract":"We present a new compilation technique for generating efficient code from synchronous programs. The main idea of our approach consists of computing for each program location an instantaneous statement (called a job) that has to be executed whenever the corresponding program location is active. Given the computed jobs, the overall execution scheme is highly flexible, very efficient, but nevertheless very simple: At each instant, it essentially consists of executing the set of active jobs according to their dynamic dependencies. Besides the required outputs, the execution of the jobs additionally yields the set of active threads for the next instant. As our translation directly follows the structure of the source code, the correctness of the translation can be easily checked by theorem provers. Furthermore, our translation scheme offers new potential for multi-processor execution, modular compilation, and multi-language code generation","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125882149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A verified development of hardware using CSP/spl par/B","authors":"A. McEwan, Steve A. Schneider","doi":"10.1109/MEMCOD.2006.1695904","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695904","url":null,"abstract":"Summary form only given. In this paper, we show a combination of the process algebra CSP and the state-based formalism B, combined into a single notation called CSPparB (pronounced CSP parallel B) being used in the formal development of reconfigurable hardware, implemented in Handel-C. The use of CSPparB and associated fools is demonstrated using a significant, realistic application. This paper is the first recorded use of CSPparB in hardware development although it has been previously used for software. The contribution of this paper may be summarised as follows: demonstration of formal CSPparB development, guided by engineering intuition and domain knowledge; evidence that CSPparB forms a feasible technology upon which to build high assurance hardware systems; examples of proof techniques and tool usage for CSPparB in giving these high levels of assurance. Development is top-down and piece-wise: refinement is from an abstract sequential specification info a highly concurrent implementation. Justification of refinement steps employs the use of control loop invariants, which are used to show the consistency of the interaction of the CSP and the B components. In introducing concurrency, additional requirements appear which could be met by software, dedicated hardware components, or by custom hardware on an FPGA. The piece-wise nature of the development allow for this choice to be postponed while other components are implemented - possibly in different technologies. The choice of where concurrency may be introduced in order to meet timing requirements, whilst still attaining reasonable area usage is guided by knowledge of the application domain and the target FPGA platform. Safety and functional properties of the abstract specification are automatically verified; theoretical results concerning refinement guarantee that these hold for the implementation. Proof obligations are discharged using the CSP model-checker FDR and the theorem prover B-Toolkit. The central conclusion of this paper is that CSPparB forms the basis of a valid technology for the exploration and development of high assurance hardware and software systems. Further research is to investigate co-design, understand how a design calculus may be incorporated, and how further automatic tool support may be provided in discharging CLI proofs","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A semantic-driven synthesis flow for platform-based design","authors":"Qi Zhu, A. Davare, A. Sangiovanni-Vincentelli","doi":"10.1109/MEMCOD.2006.1695928","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695928","url":null,"abstract":"In this work, we propose a semantics-driven synthesis flow, in which the semantics and the abstraction level are determined formally by using the concept of a common modeling domain between functionality and architecture. By doing so, a formal synthesis procedure can be defined and algorithms for automatic optimal mapping derived","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assertion checking of control dominated systems with nonlinear solvers","authors":"Í. Ugarte, P. Sánchez","doi":"10.1109/MEMCOD.2006.1695929","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695929","url":null,"abstract":"Nowadays, the verification of systems has grown to dominate the cost of electronic system design, often with limited success, as designs continue to be released with latent bugs. The International Technology Roadmap for Semiconductors (ITRS) affirms in the report of 2005 that for the most complex designs, verification engineers outnumber designers with this ratio reaching two or three to one. Assertion-based verification (ABV) is a promising methodology to confront the growing problem of system design verification (Yeung and Larsen, 2005). Key aspects in increasing the scalability of formal and semi-formal verification techniques are the role of the solver and the level of abstraction of the system description. Several assertion checking techniques based on nonlinear solvers have been proposed to verify assertions in behavioral level system descriptions. These techniques are very efficient with data dominated designs (for example digital filters) but they have a lot of problems with control dominated designs in which the variables have a small set of possible values (typically two, 0 and 1). This paper presents several techniques that allow the use of a commercial nonlinear solver to check assertions in control dominated design. And it studies in depth some techniques that allow the transformation of the behavioral level system description into a set of polynomial inequalities that efficiently model control dominated designs. The goal of the verification methodology is maximizing a nonlinear equation (the assertion equation in this paper) while satisfying a set of non-linear constraints (polynomial inequalities) that model conditional statements and discontinuous functions in this work. The commercial solver LINDO is an example of a global non-linear solver and it has been used in this work. In order to validate the proposed technique, the example 'MPEG system decoder' used by (Mitchel et al., 1997) for HW verification is selected. The system decoder is composed of several modules, completely decoupled behaviorally amongst themselves. The verification can be done individually for each module. The property \"EF (stop = \"1\") (LTL nomenclature) has to be verified to guarantee that the composite design will work. The table shows the results. These components are control dominated designs with very few data operations. The second column (non-linear) shows the CPU time of the proposed technique, while the third column presents the time of a commercial integer solver. It can be shown that the proposed technique provides similar results to an integer solver with pure control descriptions","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131854898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-power hardware synthesis from TRS-based specifications","authors":"Gaurav Singh, S. Shukla","doi":"10.1109/MEMCOD.2006.1695900","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695900","url":null,"abstract":"Synthesis from guarded atomic actions used for high-level descriptions of hardware designs has been shown to be a successful methodology for generating efficient designs (Arvind et al., 2004). This methodology uses CAOS (concurrent action oriented specifications) for hardware description which is based on the idea of term rewriting systems (TRS's) (Baader and Nipkov, 1998; Hoe and Arvind, 1999). A prime example of CAOS is Bluespec where the behavior of a design is described using various guarded atomic actions. Hardware synthesis from such specifications can infer more parallelism than is possible from the traditional methods of behavioral synthesis using CDFGs (control data-flow graphs) (Gupta et al.; Chang and Pedram, 1999; Lakshminarayana et al., 1998). Hardware implementations generated from CAOS can exploit the parallelism germane in the computation and execute maximal set of actions concurrently in order to reduce the latency of the design. The concurrent execution of the actions enhances the performance of the hardware designs in terms of the delay but high power consumption may become an issue when multiple such actions are executed concurrently. Thus, there is a need to reduce power consumption during the CAOS-based synthesis. In this paper, we consider a CAOS similar to Bluespec's model of computation and present two strategies targeting the reduction of peak power and dynamic power in designs generated from such specifications. One strategy uses the re-scheduling of the atomic actions to generate a low-power schedule whereas the other exploits the factorization as well as the re-scheduling of the actions for power reduction","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128157810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"802.11a transmitter: a case study in microarchitectural exploration","authors":"Nirav H. Dave, Michael Pellauer, Steve Gerding","doi":"10.1109/MEMCOD.2006.1695901","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695901","url":null,"abstract":"Hand-held devices have rigid constraints regarding power dissipation and energy consumption. Whether a new functionality can be supported often depends upon its power requirements. Concerns about the area (or cost) are generally addressed after a design can meet the performance and power requirements. Different micro-architectures have very different area, timing and power characteristics, and these need RTL-level models to be evaluated. In this paper we discuss the microarchitectural exploration of an 802.11a transmitter via synthesizable and highly-parameterized descriptions written in Bluespec SystemVerilog (BSV). We also briefly discuss why such architectural exploration would be practically infeasible without appropriate linguistic facilities. No knowledge of 802.11a or BSV is needed to read this paper","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114504234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design","authors":"Hiren D. Patel, S. Shukla, E. Mednick, R. Nikhil","doi":"10.1109/MEMCOD.2006.1695899","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695899","url":null,"abstract":"Bluespec's rule-based model of computation (MoC) for hardware concurrency has gained attention for several reasons. From its basis in term rewriting systems, rules have the property of atomicity, which improves correctness by construction, particularly in large-scale concurrency with finegrained, dynamic resource sharing (typical in complex hardware). Rule-based interface methods extend atomicity across module boundaries, have a natural transactional reading, and precisely and formally characterize resource-sharing constraints. All this can be synthesized to hardware with competitive quality. SystemC expresses concurrency with threading and events, just like RTL, where it is difficult to deal with fine-grain concurrency and resource sharing. Further, there is no systematic methodology for module composition. Thus, while SystemC is suitable for very coarse modeling and for embedded software development, its limitations make it difficult to model correct by construction hardware systems accurately. In this paper, we show how to integrate Bluespec's rule-based MoC into SystemC. We augment SystemC modules with rules and rule-based interface methods, and augment the SystemC simulation kernel with a rule execution kernel. The integration is augmentative in that a model can contain both rule-based modules (where hardware accuracy is desired) as well as core SystemC or TLM modules (for embedded software, instruction-set simulators, existing SystemC IP, or pure behavioral models), thus providing the advantages of each MoC where appropriate","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115153054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Latency-insensitive design and central repetitive scheduling","authors":"Julien Boucaron, R. Simone, J. Millo","doi":"10.1109/MEMCOD.2006.1695923","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695923","url":null,"abstract":"The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the inception of arbitrarily fixed (integer) latencies for data/signals traveling along wires or communication media. Then mechanisms such as shell wrappers and relay-stations are introduced to \"implement\" the necessary backpressure congestion control, so that data with shorter travel duration can safely await others with which they are to be consumed simultaneously by the same computing element. These mechanisms can themselves be efficiently represented as synchronous components in this global, asynchronously-spirited environment. Despite their efficient form, relay-stations and backpressure mechanisms add complexity to a system whose behaviour is ultimately very repetitive. Indeed, the \"slowest\" data loops regulate the traffic and organize the traffic to their pace. This specific repetitive scheduling has been extensively studied in the past under the name of \"central repetitive problem\", and results were established proving that so-called k-periodic optimal solutions could be achieved. But the \"implementation\" using typical synchronous circuit elements in the LID context was never worked out. We deal with these issues here, using explicit representation of schedules as periodic words on {0,1}* borrowed from the recently theory of N-synchronous systems","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programming models and languages for SoC-implemented architectures","authors":"Rajesh K. Gupta","doi":"10.1109/MEMCOD.2006.1695914","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695914","url":null,"abstract":"Summary form only given. Microsystems implemented on chips or SoCs provide new capabilities and alternatives not easily available to architects in the past, via ISA extensions, additional data-path elements, SIMD arrays and their short vector extensions, multigrain coprocessing etc. We can, given enough design resources, build such machines. Evidence of various combinations of architectural archetypes can be seen in a flood of new machine architectures for high definition video processing, though there are significant challenges in architectural exploration. However, a central question that seems to remain unanswered, is how will the programming for such machines can keep up without waiting for the god of programming to descend. Participants will take a crack at answering the questions either from architectural side (including implementation fabrics) or from their views of the advances in programming models and methods","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Equivalence checking: a rule-based approach","authors":"M. Fujita, S. Shankar, Sasaki Shunsuke","doi":"10.1109/MEMCOD.2006.1695926","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695926","url":null,"abstract":"A well-known problem in the design of embedded systems is checking for equivalence of two systems, and the traditional approach constructs and proves equivalence of finite state models of the two systems. Although widely and successfully used, the main problem is state space explosion, and other forms of higher-level analysis are also needed typically. Many typical system level design/synthesis tools and methodologies basically transform the control structures among function calls and/or sets of statements, with little modification to statements themselves. For example, the systems might differ only in statement order, dataflows (for differing amounts of parallelism), or abstraction levels. For such cases, we have developed an approach based on higher level static code analysis, and we have implemented a tool targeted at the SpecC language","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131937765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}