Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.最新文献

{"title":"Mixed symbolic representations for model checking software programs","authors":"Z. Yang, Chao Wang, Aarti Gupta, Franjo Ivancic","doi":"10.1109/MEMCOD.2006.1695896","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695896","url":null,"abstract":"We present an efficient symbolic search algorithm for software model checking. The algorithm combines multiple symbolic representations to efficiently represent the transition relation and reachable states and uses a combination of decision procedures for Boolean and integer representations. Our main contributions include: (1) mixed symbolic representations to model C programs with rich data types and complex expressions; and (2) new symbolic search strategies and optimization techniques specific to sequential programs that can significantly improve the scalability of model checking algorithms. Our controlled experiments on real-world software programs show that the new symbolic search algorithm can achieve several orders-of-magnitude improvements over existing methods. The proposed techniques are extremely competitive in handling sequential models of non-trivial sizes, and also compare favorably to popular Boolean-level model checking algorithms based on BDDs and SAT","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114978561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A methodology for abstracting RTL designs into TL descriptions","authors":"N. Bombieri, F. Fummi, G. Pravadelli","doi":"10.1109/MEMCOD.2006.1695911","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695911","url":null,"abstract":"Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, modeling a complex system completely at transaction level (TL) could be inconvenient when IP cores are available on the market, usually modeled at RT level. In this context, modeling and verification methodologies based on transactors allow one to reuse RTL IP-cores in TL-RTL mixed designs, thus guaranteeing a considerable saving of time. Even if practical advantages of such an approach are evident, mixed TL-RTL designs cannot completely benefit from the well-known effectiveness provided by TLM. Thus, this paper proposes a methodology to abstract RTL IPs into corresponding TL descriptions. The possibility of automating the methodology is deeply analyzed. In particular, the paper shows which abstraction levels can be reached without requiring human intervention, according to the characteristics of the design to be refined. A set of experimental results are finally reported to confirm the effectiveness of the methodology","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132837972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating design and verification - from simple idea to practical system","authors":"C. Seger","doi":"10.1109/MEMCOD.2006.1695920","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695920","url":null,"abstract":"Summary form only given. For many VLSI designs, validation has started to dominate the total design effort. In addition, historical trends are indicating that this problem will continue to grow. For example, data from Intel's lead microprocessor design efforts shows that the number of pre-silicon bugs has increased by a factor of four for every lead project for the last 25 years. If this trend is not broken, Intel's next lead design is likely to have to go through the \"find the bug, evaluate it, root cause it, fix it, and validate the fix\" process tens of thousands of times; potentially overwhelming the validation and design team. Thus one of the most critical goals for improving the design process is to break this bug trend. In the presentation, we introduce the integrated design and verification (IDV) system that has been developed at Intel for the last 5 years. IDV combines the design and validation efforts so that the task of design validation (i.e., \"Did we capture what we actually wanted?\") is significantly simplified by means of a much smaller and much more stable high-level model. Furthermore, when the design is completed, so also is the implementation validation (i.e., \"Did we implement what we intended?\"). The latter is accomplished by linking the design process very tightly with the validation process. Although this idea is not new, the combination of correct-by-construction and correct-by-verification and the tight integration of a database of verified results is new and has led to a design environment that allows rapid design in which the validation problem has been significantly reduced. To make the presentation more realistic, we will use the design, from a high-level model to layout, of a floating point execution unit as a driving example. We discuss the early design phase in which the high-level model is refined using algorithmic transformations to a viable micro architecture; continue with the middle level design in which the actual logic implementation is derived and conclude with the final placement and layout stage. Although the design process conceptually is performed sequentially, we will illustrate the tight loop that IDV enables between physical design and logical/micro-architectural design. The latter is a critical component in enabling design convergence. In fact, in today's process technology, integration of physical and logical design is not optional but rather mandatory","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121998275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Specifying and proving properties of timed I/O automata in the TIOA toolkit","authors":"M. Archer, Hong-Kyoon Lim, N. Lynch, S. Mitra, S. Umeno","doi":"10.1109/MEMCOD.2006.1695916","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695916","url":null,"abstract":"Timed I/O Automata (TIOA) is a mathematical framework for modeling and verification of distributed systems that involve discrete and continuous dynamics. TIOA can be used for example, to model a real-time software component controlling a physical process. The TIOA model is sufficiently general to subsume other models in use for timed systems. The TIOA toolkit, currently under development, is aimed at supporting system development based on TIOA specifications. The TIOA toolkit is an extension of the IOA toolkit, which provides a specification simulator, a code generator, and both model checking and theorem proving support for analyzing specifications. This paper focuses on modeling of timed systems with TIOA and the TAME-based theorem proving support provided in the toolkit, for proving system properties, including timing properties. Several examples are provided by way of illustration","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132451293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using Reo for formal specification and verification of system designs","authors":"N. Razavi, M. Sirjani","doi":"10.1109/MEMCOD.2006.1695912","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695912","url":null,"abstract":"In this paper, we introduce a component-based approach to specify and verify system-level designs. A coordination language, Reo, is used to support hierarchical design and verification. We move from functional specification to implementation through different levels of abstraction, considering TLM/RTL mixed levels and hardware/software co-designs. We discuss the mapping of a system design written in SystemC to Reo circuits, and how we can compositionally construct its behavior using constraint automata. A case study is used to show the applicability of our approach","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117290620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Execution semantics and formalisms for multi-abstraction TLM assertions","authors":"W. Ecker, Volkan Esen, M. Hull","doi":"10.1109/MEMCOD.2006.1695910","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695910","url":null,"abstract":"Electronic system level (ESL) reflects the current trend in hardware design and verification towards abstraction levels higher than RTL referred to as transaction level (TL). Raising the abstraction level leads to reduced complexity compared to classical RTL modeling; however, due to this lack of detail, verification of higher level models produces new problems. Assertion based verification (ABV) - a well established RTL methodology - is a good example of this. Temporal relations in RTL properties are specified in terms of clocks that trigger the design. It is not obvious how to specify properties for more abstract, non-clocked models where the notion of lime is annotated as estimated delay values or omitted completely. Since ABV has already shown to be a strong methodology for functional RTL verification, we expect the same benefit for TL by lifting current ABV approaches to a higher level. In this paper we present a prototypic formal framework for specifying TL properties. We focus our work on three TL model views, as defined in the OSCI TLM standard. For each view we describe the model of computation and derive the required operators. Furthermore, we explain the required execution semantics and give some application examples","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125001727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A scenario-aware data flow model for combined long-run average and worst-case performance analysis","authors":"B. Theelen, M. Geilen, T. Basten, J. Voeten, S. V. Gheorghita, S. Stuijk","doi":"10.1109/MEMCOD.2006.1695924","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695924","url":null,"abstract":"Data flow models are used for specifying and analysing signal processing and streaming applications. However, traditional data flow models are either not capable of expressing the dynamic aspects of modern streaming applications or they do not support relevant analysis techniques. The dynamism in modern streaming applications often originates from different modes of operation (scenarios) in which data production and consumption rates and/or execution times may differ. This paper introduces a scenario-aware generalisation of the synchronous data flow model, which uses a stochastic approach to model the order in which scenarios occur. The formally defined operational semantics of a scenario-aware data flow model implies a Markov chain, which can be analysed for both long-run average and worst-case performance metrics using existing exhaustive or simulation-based techniques. The potential of using scenario-aware data flow models for performance analysis of modern streaming applications is illustrated with an MPEG-4 decoder example","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132291189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"R-SHIM: deterministic concurrency with recursion and shared variables","authors":"O. Tardieu, S. Edwards","doi":"10.1109/MEMCOD.2006.1695931","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695931","url":null,"abstract":"Concurrent programming languages are good for embedded systems because they match the parallelism of their environments, but most concurrent languages are nondeterministic, making coding in them unwieldy. We present R-SHIM, the core of a language with concurrent recursive procedure calls and disciplined shared variables that remains deterministic - the behavior of a program is scheduling-independent","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131923978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analyzing tabular requirements specifications using infinite state model checking","authors":"T. Bultan, C. Heitmeyer","doi":"10.1109/MEMCOD.2006.1695895","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695895","url":null,"abstract":"This paper investigates the application of infinite state model checking to the formal analysis of requirements specifications in the SCR (software cost reduction) tabular notation using action language verifier (ALV). After reviewing the SCR method and tools and the action language, experimental results are presented of formally analyzing two SCR specifications using ALV, The application of ALV to verify or falsify (by generating counterexamples) the state and transition invariants of SCR specifications and to check disjointness and coverage properties is described. ALV is compared with the verification techniques that have been integrated into the SCR toolset","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128825716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic decomposition for sequential equivalence checking of system level and RTL descriptions","authors":"Shobha Vasudevan, J. Abraham, V. Viswanath, Jiajin Tu","doi":"10.1109/MEMCOD.2006.1695903","DOIUrl":"https://doi.org/10.1109/MEMCOD.2006.1695903","url":null,"abstract":"Sequential equivalence checking between system level descriptions of designs and their register transfer level (RTL) implementations is a very challenging and important problem in the context of systems on a chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in system level languages or hardware description languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a SystemC description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC","PeriodicalId":301159,"journal":{"name":"Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123510553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}