Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)最新文献_第3页

Decoupling local variable accesses in a wide-issue superscalar processor 大问题超标量处理器中局部变量访问的解耦

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765943

Sangyeun Cho, P. Yew, Gyungho Lee

{"title":"Decoupling local variable accesses in a wide-issue superscalar processor","authors":"Sangyeun Cho, P. Yew, Gyungho Lee","doi":"10.1109/ISCA.1999.765943","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765943","url":null,"abstract":"Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data cache however becomes increasingly inefficient and can add to the hardware complexity significantly. This paper takes an alternative or complementary approach for providing more data bandwidth, called the data-decoupled architecture. The approach, with support from the compiler and/or hardware, partitions the memory stream into two independent streams early in the processor pipeline, and feeds each stream to a separate memory access queue and cache. Under this model, the paper studies the potential of decoupling memory accesses to program's local variables that are allocated on the run-time stack. Using a set of integer and floating-point programs from the SPEC95 benchmark suite, it is shown that local variable accesses constitute a large portion of all the memory references, while their reference space is very small, averaging around 7 words per (static) procedure. To service local variable accesses quickly, two optimizations fast data forwarding and access combining, are proposed and studied. Some of the important design parameters, such as the cache size, the number of cache ports, and the degree of access combining, are studied based on simulations. The potential performance of the proposed scheme is measured using various configurations, and it is concluded that the scheme can become a viable alternative to building a single multi-ported data cache.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132329715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 58

Memory forwarding: enabling aggressive layout optimizations by guaranteeing the safety of data relocation 内存转发:通过保证数据重定位的安全性，实现激进的布局优化

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765942

C. Luk, T. Mowry

{"title":"Memory forwarding: enabling aggressive layout optimizations by guaranteeing the safety of data relocation","authors":"C. Luk, T. Mowry","doi":"10.1109/ISCA.1999.765942","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765942","url":null,"abstract":"By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache conflicts and false sharing. Unfortunately, it is extremely difficult to guarantee that such optimizations are safe in practice on today's machines, since accurately updating all pointers to an object requires perfect alias information, which is well beyond the scope of the compiler for languages such as C. To overcome this limitation, we propose a technique called memory forwarding which effectively adds a new layer of indirection within the memory system whenever necessary to guarantee that data relocation is always safe. Because actual forwarding rarely occurs (it exists as a safety net), the mechanism can be implemented as an exception in modern superscalar processors. Our experimental results demonstrate that the aggressive layout optimizations enabled by memory forwarding can result in significant speedups-more than twofold in some cases-by reducing the number of cache misses, improving the effectiveness of prefetching, and conserving memory bandwidth.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116789342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51

Storageless value prediction using prior register values 使用先前寄存器值的无存储值预测

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765957

D. Tullsen, J. Seng

引用次数: 81

Effective jump-pointer prefetching for linked data structures 链接数据结构的有效跳转指针预取

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765944

A. Roth, G. Sohi

引用次数: 202

Selective value prediction 选择性值预测

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765940

B. Calder, Glenn D. Reinman, D. Tullsen

引用次数: 216

Area efficient architectures for information integrity in cache memories 区域高效架构的信息完整性在高速缓存存储器

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765955

Seongwoo Kim, Arun Kumar Somani

{"title":"Area efficient architectures for information integrity in cache memories","authors":"Seongwoo Kim, Arun Kumar Somani","doi":"10.1109/ISCA.1999.765955","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765955","url":null,"abstract":"Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it difficult to trade between the level of data integrity and the chip area requirement. We focus on transient fault tolerance in primary cache memories and develop new architectural solutions to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code. The underlying idea is to exploit the corollary of reference locality in the organization and management of the code. A higher protection priority is dynamically assigned to the portions of the cache that are more error-prone and have a higher probability of access. The error-prone likelihood prediction is based on the access frequency. We evaluate the effectiveness of the proposed schemes using a trace-driven simulation combined with software error injection using four different fault manifestation models. From the simulation results, we show that for most benchmarks the proposed architectures are effective and area efficient for increasing the cache integrity under all four models.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134017192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 110