Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)最新文献_第2页

Maps: a compiler-managed memory system for Raw machines map:用于Raw机器的编译器管理的内存系统

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1145/300979.300980

R. Barua, Walter Lee, Saman P. Amarasinghe, A. Agarwal

{"title":"Maps: a compiler-managed memory system for Raw machines","authors":"R. Barua, Walter Lee, Saman P. Amarasinghe, A. Agarwal","doi":"10.1145/300979.300980","DOIUrl":"https://doi.org/10.1145/300979.300980","url":null,"abstract":"This paper describes Maps, a compiler managed memory system for Raw architectures. Traditional processors for sequential programs maintain the abstraction of a unified memory by using a single centralized memory system. This implementation leads to the infamous \"Von Neumann bottleneck,\" with machine performance limited by the large memory latency and limited memory bandwidth. A Raw architecture addresses this problem by taking advantage of the rapidly increasing transistor budget to move much of its memory on chip. To remove the bottleneck and complexity associated with centralized memory, Raw distributes the memory with its processing elements. Unified memory semantics are implemented jointly by the hardware and the compiler. The hardware provides a clean compiler interface to its two inter-tile interconnects: a fast, statically schedulable network and a traditional dynamic network. Maps then uses these communication mechanisms to orchestrate the memory accesses for low latency and parallelism while enforcing proper dependence. It optimizes for speed in two ways: by finding accesses that can be scheduled on the static interconnect through static promotion, and by minimizing dependence sequentialization for the remaining accesses. Static promotion is performed using equivalence class unification and module unrolling: memory dependences are enforced through explicit synchronization and software serial ordering. We have implemented Maps based on the SUIF infrastructure. This paper demonstrates that the exclusive use of static promotion yields roughly 20-fold speedup on 32 tiles for our regular applications and about 5-fold speedup on 16 or more tiles for our irregular applications. The paper also shows that selective use of dynamic accesses can be a useful complement to the mostly static memory system.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134427852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 105

Is SC+ILP=RC? 独立是SC + = RC ?

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765948

C. Gniady, B. Falsafi, T. N. Vijaykumar

{"title":"Is SC+ILP=RC?","authors":"C. Gniady, B. Falsafi, T. N. Vijaykumar","doi":"10.1109/ISCA.1999.765948","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765948","url":null,"abstract":"Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high performance implementations. Release consistency (RC), however, enables the highest performance implementations but puts the burden on the programmer to specify which memory operations need to be atomic and in program order. This paper shows, for the first time, that SC implementations can perform as well as RC implementations if the hardware provides enough support for speculation. Both SC and RC implementations rely on reordering and overlapping memory operations for high performance. To enforce order when necessary, an RC implementation uses software guarantees, whereas an SC implementation relies on hardware speculation. Our SC implementation, called SC++, closes the performance gap because: (1) the hardware allows not just loads, as some current SC implementations do, but also stores to bypass each other speculatively to hide remote latencies, (2) the hardware provides large speculative state for not just processor, as previously proposed, but also memory to allow out-of-order memory operations, (3) the support for hardware speculation does not add excessive overheads to processor pipeline critical paths, and (4) well-behaved applications incur infrequent rollbacks of speculative execution. Using simulation, we show that SC++ achieves an RC implementation's performance in all the six applications we studied.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132585669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 174

Memory sharing predictor: the key to a speculative coherent DSM 内存共享预测器:推测性连贯DSM的关键

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765949

An-Chow Lai, B. Falsafi

{"title":"Memory sharing predictor: the key to a speculative coherent DSM","authors":"An-Chow Lai, B. Falsafi","doi":"10.1109/ISCA.1999.765949","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765949","url":null,"abstract":"Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately predicting a message and timely invoking the necessary coherence actions, a DSM can hide much of the remote access latency. This paper proposes the Memory Sharing Predictors (MSPs), pattern-based predictors that significantly improve prediction accuracy and implementation cost over general message predictors. An MSP is based on the key observation that to hide the remote access latency, a predictor must accurately predict only the remote memory accesses (i.e., request messages) and not the subsequent coherence messages invoked by an access. Simulation results indicate that MSPs improve prediction accuracy over general message predictors from 81% to 93% while requiring less storage overhead. This paper also presents the first design and evaluation for a speculative coherent DSM using pattern-based predictors. We identify simple techniques and mechanisms to trigger prediction timely and perform speculation for remote read accesses. Our speculation hardware readily works with a conventional full-map write-invalidate coherence protocol without any modifications. Simulation results indicate that performing speculative read requests alone reduces execution times by 12% in our shared-memory applications.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116556430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 106

Value prediction in VLIW machines VLIW机器中的值预测

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765956

T. Nakra, Rajiv Gupta, M. Soffa

{"title":"Value prediction in VLIW machines","authors":"T. Nakra, Rajiv Gupta, M. Soffa","doi":"10.1109/ISCA.1999.765956","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765956","url":null,"abstract":"The performance of VLIW architectures is dependent on the capability of the compiler to detect and exploit instruction-level parallelism during instruction scheduling. To exploit the detected parallelism, instructions are reordered to reduce the length of the code schedule and minimize the cycle count for execution. Code reordering is limited by the dependencies among instructions arising from both control flow and data flow. In this paper, we present the design of a VLIW architecture that uses value prediction to remove data dependencies and improve the instruction schedule. Our architecture consists of two execution engines, one for executing the original VLIW code, and the other for executing compensation code after a misprediction. Any code executed due to mispredictions is executed in parallel with the VLIW instructions. The instruction set and hardware of a traditional VLIW machine are modified accordingly to support this type of concurrent execution. The efficacy of the proposed architecture is demonstrated by implementing the prediction model in the Trimaran compiler infrastructure and studying the speedups that result due to the parallel execution of compensation code.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133797438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Multicast snooping: a new coherence method using a multicast address network 组播窥探:一种利用组播地址网络的相干性方法

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765959

Ender Bilir, Ross Dic kson, Ying Hu, Manoj Plakal, Daniel J. Sorin, M. Hill, Da vid Wood

{"title":"Multicast snooping: a new coherence method using a multicast address network","authors":"Ender Bilir, Ross Dic kson, Ying Hu, Manoj Plakal, Daniel J. Sorin, M. Hill, Da vid Wood","doi":"10.1109/ISCA.1999.765959","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765959","url":null,"abstract":"This paper proposes a new coherence method called \"multicast snooping\" that dynamically adapts between broadcast snooping and a directory protocol. Multicast snooping is unique because processors predict which caches should snoop each coherence transaction by specifying a multicast \"mask\". Transactions are delivered with an ordered multicast network, such as an Isotach network, which eliminates the need for acknowledgment messages. Processors handle transactions as they would with a snooping protocol while a simplified directory operates in parallel to check masks and gracefully handle incorrect ones (e.g., previous owner missing). Preliminary performance numbers with mostly SPLASH-2 benchmarks running on 32 processors show that we can limit multicasts to an average of 2-6 destinations (/spl Lt/ 32) and we can deliver 2-5 multicasts per network cycle (/spl Gt/ broadcast snooping's 1 per cycle). While these results do not include timing, they do provide encouragement that multicast snooping can obtain data directly (like broadcast snooping) but apply to larger systems (like directories).","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133929784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 106

Performance of image and video processing with general-purpose processors and media ISA extensions 使用通用处理器和媒体ISA扩展的图像和视频处理性能

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765945

Parthasarathy Ranganathan, S. Adve, N. Jouppi

{"title":"Performance of image and video processing with general-purpose processors and media ISA extensions","authors":"Parthasarathy Ranganathan, S. Adve, N. Jouppi","doi":"10.1109/ISCA.1999.765945","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765945","url":null,"abstract":"This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without and with media ISA extensions. We use detailed simulation of 12 benchmarks to study the effectiveness of current architectural features and identify future challenges for these workloads. Our results show that conventional techniques in current processors to enhance instruction-level parallelism (ILP) provide a factor of 2.3 X to 4.2 X performance improvement. The Sun VIS media ISA extensions provide an additional 1.1 X to 4.2 X performance improvement. The ILP features and media ISA extensions significantly reduce the CPU component of execution time, making 5 of the image processing benchmarks memory-bound. The memory behavior of our benchmarks is characterized by large working sets and streaming data accesses. Increasing the cache size has no impact on 8 of the benchmarks. The remaining benchmarks require relatively large cache sizes (dependent on the display sizes) to exploit data reuse, but derive less than 1.2 X performance benefits with the larger caches. Software prefetching provides 1.4 X to 2.5 X performance improvement in the image processing benchmarks where memory is a significant problem. With the addition of software prefetching, all our benchmarks revert to being compute-bound.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115525049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 177

Commit-Reconcile and Fences (CRF): a new memory model for architects and compiler writers 提交-调和和隔离(CRF):一种面向架构师和编译器编写者的新内存模型

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765947

Xiaowei Shen, Arvind, L. Rudolph

引用次数: 74

Scaling application performance on a cache-coherent multiprocessors 在缓存一致的多处理器上扩展应用程序性能

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765960

Dongming Jiang, J. Singh

{"title":"Scaling application performance on a cache-coherent multiprocessors","authors":"Dongming Jiang, J. Singh","doi":"10.1109/ISCA.1999.765960","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765960","url":null,"abstract":"Hardware-coherent, distributed shared address space systems are increasingly successful at moderate scale. However, it is unclear whether, or with how much difficulty, the performance of a load-store shared address space programming model scales to large processor counts on real applications. We examine this question using an aggressive case-study machine, the SGI Origin2000, up to 128 processors. We show for the first time that scalable performance can indeed be achieved in this programming model on a wide range of applications, including challenging kernels like FFT. However, this does not come easily, even for applications considered to be already highly optimized, and is very often not simply a matter of increasing problem size. Rather, substantial further application restructuring is often needed, which is usually quite algorithmic in nature. We examine how the restructurings compare with those needed for performance portability to shared virtual memory on clusters, and we comment on common programming guidelines for performance portability and scalability as well as on how the programming difficulty compares with that of explicit message passing. We also examine where applications spend their time on this large machine, the impact of special hardware features that the machine provides, and the impact of mapping to the network topology.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 61

PipeRench: a coprocessor for streaming multimedia acceleration PipeRench:用于流媒体加速的协处理器

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765937

S. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. Taylor, R. Laufer

引用次数: 444

Simultaneous subordinate microthreading (SSMT) 同步从属微线程(SSMT)

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765950

R. Chappell, J. Stark, Sangwook P. Kim, S. Reinhardt, Y. Patt

引用次数: 254