Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)最新文献

A performance comparison of contemporary DRAM architectures 当代DRAM架构的性能比较

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1145/300979.300998

V. Cuppu, B. Jacob, B. Davis, T. Mudge

引用次数: 227

Correlated load-address predictors 相关负载地址预测器

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765939

Michael Bekerman, S. Jourdan, R. Ronen, G. Kirshenboim, Lihu Rappoport, A. Yoaz, U. Weiser

{"title":"Correlated load-address predictors","authors":"Michael Bekerman, S. Jourdan, R. Ronen, G. Kirshenboim, Lihu Rappoport, A. Yoaz, U. Weiser","doi":"10.1109/ISCA.1999.765939","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765939","url":null,"abstract":"As microprocessors become faster, the relative performance cost of memory accesses increases. Bigger and faster caches significantly reduce the absolute load-to-use time delay. However, increase in processor operational frequencies impairs the relative load-to-use latency, measured in processor cycles (e.g. from two cycles on the Pentium processor to three cycles of more in current designs). Load-address prediction techniques were introduced to partially cut the load-to-use latency. This paper focuses on advanced address-prediction schemes to further shorten program execution time. Existing address prediction schemes are capable of predicting simple address patterns, consisting mainly of constant addresses or stride-based addresses. This paper explores the characteristics of the remaining loads and suggests new enhanced techniques to improve prediction effectiveness: Context-based prediction to tackle part of the remaining, difficult-to-predict, load instructions. New prediction algorithms to take advantage of global correlation among different static loads. New confidence mechanisms to increase the correct prediction rate and to eliminate costly mispredictions. Mechanisms to prevent long or random address sequences from polluting the predictor data structures while providing some hysteresis behavior to the predictions. Such an enhanced address predictor accurately predicts 67% of all loads, while keeping the misprediction rate close to 1% We further prove that the proposed predictor works reasonably well in a deep pipelined architecture where the predict-to-update delay may significantly impair both prediction rate and accuracy.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127250710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 106

The program decision logic approach to predicated execution 将程序决策逻辑方法用于预测执行

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765952

David I. August, J. Sias, Jean-Michel Puiatti, S. Mahlke, D. Connors, K. Crozier, W. Hwu

{"title":"The program decision logic approach to predicated execution","authors":"David I. August, J. Sias, Jean-Michel Puiatti, S. Mahlke, D. Connors, K. Crozier, W. Hwu","doi":"10.1109/ISCA.1999.765952","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765952","url":null,"abstract":"Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has translated the programmer's original control structure directly into assembly code with conditional branch instructions. Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research. However, traditional branch handling techniques cannot significantly alter the program's inherent control structure. The advent of predication as a program control representation has enabled compilers to manipulate control in a form more closely related to the underlying program logic. This work takes full advantage of the predication paradigm by abstracting the program control flow into a logical form referred to as a program decision logic network. This network is modeled as a Boolean equation and minimized using modified versions of logic synthesis techniques. After minimization, the more efficient version of the program's original control flow is re-expressed in predicated code. Furthermore, this paper proposes extensions to the HPL PlayDoh predication model in support of more effective predicate decision logic network minimization. Finally, this paper shows the ability of the mechanisms presented to overcome limits on ILP previously imposed by rigid program control structure.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129821897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

Using network interface support to avoid asynchronous protocol processing in shared virtual memory systems 使用网络接口支持来避免共享虚拟内存系统中的异步协议处理

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765958

A. Bilas, Cheng Liao, J. Singh

{"title":"Using network interface support to avoid asynchronous protocol processing in shared virtual memory systems","authors":"A. Bilas, Cheng Liao, J. Singh","doi":"10.1109/ISCA.1999.765958","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765958","url":null,"abstract":"The performance of page-based software shared virtual memory (SVM) is still far from that achieved on hardware-coherent distributed shared memory (DSM) systems. The interrupt cost for asynchronous protocol processing has been found to be a key source of performance loss and complexity. This paper shows that by providing simple and general support for asynchronous message handling in a commodity network interface (NI), and by altering SVM protocols appropriately, protocol activity can be decoupled from asynchronous message handling and the need for interrupts or polling can be eliminated. The NI mechanisms needed are generic, not SVM-dependent. They also require neither visibility into the node memory system nor code instrumentation to identify memory operations. We prototype the mechanisms and such a synchronous home-based LRC protocol, called GeNIMA (GEneral-purpose Network Interface support in a shared Memory Abstraction), on a cluster of SMPs with a programmable NI, though the mechanisms are simple and do not require programmability. We find that the performance improvements are substantial, bringing performance on a small-scale SMP cluster much closer to that of hardware-coherent shared memory for many applications, and we show the value of each of the mechanisms in different applications. Application performance improves by about 37% on average for reasonably well performing applications, even on our relatively slow programmable NI, and more for others. We discuss the key remaining bottlenecks at the protocol level and use a firmware performance monitor in the NI to understand the interactions with and the implications for the communication layer.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126906317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

The block-based trace cache 基于块的跟踪缓存

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1145/300979.300996

B. Black, Bohuslav Rychlik, John Paul Shen

引用次数: 77

Dynamic vectorization: a mechanism for exploiting far-flung ILP in ordinary programs 动态矢量化:一种在普通程序中利用远程ILP的机制

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1145/300979.300981

S. Vajapeyam, P. Joseph, T. Mitra

{"title":"Dynamic vectorization: a mechanism for exploiting far-flung ILP in ordinary programs","authors":"S. Vajapeyam, P. Joseph, T. Mitra","doi":"10.1145/300979.300981","DOIUrl":"https://doi.org/10.1145/300979.300981","url":null,"abstract":"Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynamic vectorization (DV), as a tool for quickly building up a large logical instruction window. Dynamic vectorization converts repetitive dynamic instruction sequences into vector form, enabling the processing of instructions from beyond the corresponding program loop to be overlapped with the loop. This enables vector-like execution of programs with relatively complex static control flow that may not be amenable to static, compile time vectorization. Experimental evaluation shows that a large fraction of the dynamic instructions of four of the six SPECInt92 programs can be captured in vector form. Three of these programs exhibit significant potential for ILP improvements from dynamic vectorization, with speedups of more than a factor of 2 in a scenario of realistic branch prediction and perfect memory disambiguation. Under perfect branch prediction conditions, a fourth program also shows well over a factor of 2 speedup from DV. The speedups are due to the overlap of post-loop processing with loop processing.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132514233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Tolerating late memory traps in ILP processors 在ILP处理器中容忍后期内存陷阱

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1145/300979.300986

Xiaogang Qiu, M. Dubois

{"title":"Tolerating late memory traps in ILP processors","authors":"Xiaogang Qiu, M. Dubois","doi":"10.1145/300979.300986","DOIUrl":"https://doi.org/10.1145/300979.300986","url":null,"abstract":"ILP processors can execute a large number of instructions at the same time. Thus it becomes more and more difficult to support traps efficiently. On the other hand a current trend in architecture is to support various memory functions in software rather than hardware, usually by trapping the execution processor on a cache miss, TLB miss or a failed access to a local or remote memory. These late memory traps block the faulty instruction at the top of the active list, backing up the pipeline. Moreover the support for late memory traps may affect the performance of non-faulting memory instructions as well. In this paper we analyze the overhead caused by late memory traps in ILP processors and define several measures for this overhead. In order to tolerate late memory traps, we propose hardware prefetching of exception conditions and a tagged store buffer to implement deferred traps on stores. We show that, with these hardware optimizations, the overhead added by the lateness of traps is significantly reduced relative to the overhead of early traps. Because of caching effects the frequency of late memory traps usually decreases as they are taken deeper in the memory hierarchy and their overall impact on the execution time becomes negligible.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116161488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

A scalable front-end architecture for fast instruction delivery 用于快速指令传递的可伸缩前端架构

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765954

Glenn D. Reinman, T. Austin, B. Calder

{"title":"A scalable front-end architecture for fast instruction delivery","authors":"Glenn D. Reinman, T. Austin, B. Calder","doi":"10.1109/ISCA.1999.765954","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765954","url":null,"abstract":"In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses, branch mispredictions, and taken branches in the instruction stream. To further complicate matters, a VLSI interconnect scaling trend is materializing that further limits the performance of front-end designs in future generation process technologies. To counter these challenges, we present a fetch architecture that permits a faster cycle time than previous designs and scales better with future process technologies. Our design, called the Fetch Target Buffer, is a multi-level fetch block-oriented predictor. We decouple the FTB from the instruction fetch and decode pipelines to afford it the fastest clock possible. Through cycle-based simulation and circuit level delay analysis, we find that our multi-level FTB design is capable of delivering instructions 25% faster than the best single-level BTB-based pipeline configuration. Moreover we show that our design scales better to future process technologies than traditional single-level designs.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125871100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 114

Speculation techniques for improving load related instruction scheduling 改进负载相关指令调度的推测技术

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765938

A. Yoaz, M. Erez, R. Ronen, S. Jourdan

{"title":"Speculation techniques for improving load related instruction scheduling","authors":"A. Yoaz, M. Erez, R. Ronen, S. Jourdan","doi":"10.1109/ISCA.1999.765938","DOIUrl":"https://doi.org/10.1109/ISCA.1999.765938","url":null,"abstract":"State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-of-order engine, the instruction scheduler is responsible for dispatching instructions to execution units based on dependencies, latencies, and resource availability. Most existing instruction schedulers are doing a less than optimal job of scheduling memory accesses and instructions dependent on them, for the following reasons: Memory dependencies cannot be resolved prior to execution, so loads are not advanced ahead of preceding stores. The dynamic latencies of load instructions are unknown, so scheduling dependent instructions is based on either optimistic load-use delay (may cause re-scheduling and re-execution) or pessimistic delay (creating unnecessary delays). Memory pipelines are more expensive than other execution units, and as such, are a scarce resource. Currently, an increase in the memory execution bandwidth is usually achieved through multi-banked caches where bank conflicts limit efficiency. In this paper we present three techniques to address these scheduler limitations. One is to improve the scheduling of load instructions by using a simple memory disambiguation mechanism. The second is to improve the scheduling of load dependent instructions by employing a Data Cache Hit-Miss Predictor to predict the dynamic load latencies. And the third is to improve the efficiency of load scheduling in a multi-banked cache through cache-bank prediction.","PeriodicalId":300853,"journal":{"name":"Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116121643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 156

A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization 一个硬件驱动的分析方案，用于识别程序热点以支持运行时优化

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) Pub Date : 1999-05-02 DOI: 10.1109/ISCA.1999.765946

M. Merten, A. Trick, C. N. George, J. Gyllenhaal, W. Hwu

引用次数: 147