International Conference on Hardware/Software Codesign and System Synthesis最新文献_第8页

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors 可配置多处理器的系统级任务分配和配置选择的产量最大化

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450192

L. Singhal, Sejong Oh, E. Bozorgzadeh

{"title":"Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors","authors":"L. Singhal, Sejong Oh, E. Bozorgzadeh","doi":"10.1145/1450135.1450192","DOIUrl":"https://doi.org/10.1145/1450135.1450192","url":null,"abstract":"Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Static analysis for fast and accurate design space exploration of caches 静态分析用于快速、准确地设计空间探索缓存

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450159

Yun Liang, T. Mitra

{"title":"Static analysis for fast and accurate design space exploration of caches","authors":"Yun Liang, T. Mitra","doi":"10.1145/1450135.1450159","DOIUrl":"https://doi.org/10.1145/1450135.1450159","url":null,"abstract":"Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit rates. However, simulation is too slow to be deployed in the design space exploration, specially when it involves hundreds of design points and huge traces or long program execution. In this paper, we propose a novel static analysis technique for rapid and accurate design space exploration of instruction caches. Given the program control flow graph (CFG) annotated only with basic block and control flow edge execution counts, our analysis estimates the hit rates for multiple cache configurations in one pass. We achieve this by modeling the cache states at each node of the CFG in probabilistic manner and exploiting the structural similarities among related cache configurations. Experimental results indicate that our analysis is 24--3,855 times faster compared to the fastest known cache simulator while maintaining high accuracy (0.7% average error), in predicting hit rates for popular embedded benchmarks.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130967378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Specification and OS-based implementation of self-adaptive, hardware/software embedded systems 规范和基于操作系统的自适应，硬件/软件嵌入式系统的实现

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450151

Yvan Eustache, J. Diguet

{"title":"Specification and OS-based implementation of self-adaptive, hardware/software embedded systems","authors":"Yvan Eustache, J. Diguet","doi":"10.1145/1450135.1450151","DOIUrl":"https://doi.org/10.1145/1450135.1450151","url":null,"abstract":"This paper presents our solution for specifying and implementing self-adaptivness within an OS-based and reconfigurable embedded system according to objectives such as quality of service (QoS), performance or power consumption. More precisely, we detail our approach to separate, at runtime, application-specific decisions and hardware/software implementation decisions at system level. The first ones are related to the control of the efficiency of applications, they are specified in Local Configuration Managers (LCM) based on the knowledge of application engineers. The second ones are generic and address the choice between various hardware and software implementations according to observations of the gap between online measurements and objectives set by the user, these decisions are implemented in the Global Configuration Manager (GCM) as an adaptive close-loop model. We have designed a video tracking application on an FPGA to demonstrate the effectiveness of our solution, results are given for a system built around a NIOS soft-core with ¼COS II RTOS and new services for managing hardware and soft-ware tasks transparently.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131102165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs 异构多核asic并行机Anton的仿真与嵌入式软件开发

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450165

J. P. Grossman, C. Young, Joseph A. Bank, Kenneth M. Mackenzie, D. Ierardi, J. Salmon, R. Dror, D. Shaw

{"title":"Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs","authors":"J. P. Grossman, C. Young, Joseph A. Bank, Kenneth M. Mackenzie, D. Ierardi, J. Salmon, R. Dror, D. Shaw","doi":"10.1145/1450135.1450165","DOIUrl":"https://doi.org/10.1145/1450135.1450165","url":null,"abstract":"Anton, a special-purpose parallel machine currently under construction, is the result of a significant hardware-software codesign effort that relied heavily on an architectural simulator. One of this simulator's many important roles is to support the development of embedded software (software that runs on Anton's ASICs), which is challenging for several reasons. First, the Anton ASIC is a heterogeneous multicore system-on-a-chip, with three types of embedded cores tightly coupled to special-purpose hardware units. Second, a standard 512-ASIC configuration contains a total of 6,656 distinct embedded cores, all of which must be explicitly modeled within the simulator. Third, a portion of the embedded software is dynamically generated at simulation time.\u0000 This paper discusses the various ways in which the Anton simulator addresses these challenges. We use a hardware abstraction layer that allows embedded software source code to be compiled without modification for either the simulation host or the hardware target. We report on the effectiveness of embedding golden-model testbenches within the simulator to verify embedded software as it runs. We also describe our hardware-software cosimulation strategy for dynamically generated embedded software. Finally, we use a methodology that we refer to as concurrent mixed-level simulation to model embedded cores within massively parallel systems. These techniques allow the Anton simulator to serve as an efficient platform for embedded software development.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126652579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Methodology for multi-granularity embedded processor power model generation for an ESL design flow 面向ESL设计流程的多粒度嵌入式处理器功率模型生成方法

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450194

Young-Hwan Park, S. Pasricha, F. Kurdahi, N. Dutt

引用次数: 11

Power reduction via macroblock prioritization for power aware H.264 video applications 通过宏块优先级降低功耗的H.264视频应用

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450195

Michael A. Baker, V. Parameswaran, Karam S. Chatha, Baoxin Li

{"title":"Power reduction via macroblock prioritization for power aware H.264 video applications","authors":"Michael A. Baker, V. Parameswaran, Karam S. Chatha, Baoxin Li","doi":"10.1145/1450135.1450195","DOIUrl":"https://doi.org/10.1145/1450135.1450195","url":null,"abstract":"As the importance of multimedia applications in hand-held devices increases, the computational strain and corresponding demand for energy in such devices continues to grow. Portable multimedia devices with inherently limited energy supplies face tight energy constraints and require optimization for energy conservation. Power-aware applications give their users flexibility to prioritize and trade between performance and battery-life.\u0000 This paper introduces a power-aware technique for user selectable power reduction in exchange for controlled reductions in video quality for H.264 video streams. The technique uses an encoder-decoder pair. The encoder characterizes video streams and provides information to the decoder via Flexible Macroblock Ordering (FMO) by generating prioritized slice groups. The decoder selectively ignores low priority slice groups based on user selected preference effectively reducing the decoder workload. With a reduced computational requirement, processor voltage and frequency scaling (DVFS) significantly improve decoder power performance within timing constraints. Our PXA270 system implementation resulted in power savings of as much as 53% with an average PSNR per frame of 24dB compared to the unmodified video.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Profiling of lossless-compression algorithms for a novel biomedical-implant architecture 一种新型生物医学植入体结构的无损压缩算法分析

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450160

C. Strydis, G. Gaydadjiev

引用次数: 10

Highly-cited ideas in system codesign and synthesis 在系统协同设计和综合中被高度引用的思想

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450178

F. Vahid, T. Givargis

引用次数: 2

A performance-oriented hardware/software partitioning for datapath applications 用于数据路径应用程序的面向性能的硬件/软件分区

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450149

L. Frigerio, F. Salice

引用次数: 0

A security monitoring service for NoCs noc的安全监控服务

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450180

Leandro Fiorin, G. Palermo, C. Silvano

引用次数: 76