International Conference on Hardware/Software Codesign and System Synthesis最新文献_第10页

Intra- and inter-processor hybrid performance modeling for MPSoC architectures MPSoC架构的处理器内和处理器间混合性能建模

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450156

Frank E. B. Ophelders, S. Chakraborty, H. Corporaal

{"title":"Intra- and inter-processor hybrid performance modeling for MPSoC architectures","authors":"Frank E. B. Ophelders, S. Chakraborty, H. Corporaal","doi":"10.1145/1450135.1450156","DOIUrl":"https://doi.org/10.1145/1450135.1450156","url":null,"abstract":"The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance modeling techniques. Here, the idea is to apply different modeling and analysis techniques to different subsystems/components of an architecture/application. Such hybrid techniques often turn out to be more efficient and accurate compared to relying on a single analysis technique for the entire system. However, the challenge associated with this approach is to combine the different analysis results effectively to obtain conservative performance estimates for the entire system. In this paper we study a hybrid scheme where certain system components are simulated (e.g. using instruction set simulators), whereas others are analyzed using a formal technique called Real-Time Calculus (RTC). The main novelty of our approach stems from our use of this hybrid technique even for multiple tasks mapped onto a single processing element. In contrast to this, previous approaches relied on either full simulation or RTC-based analysis for an entire architectural component (e.g. a processor or a bus). The techniques we develop in this paper therefore allow for both intra- and inter-processor hybrid performance modeling and show how the different analysis results can be combined to efficiently obtain tight performance estimates for complex MPSoC architectures. We demonstrate the usefulness of this approach using an MPEG-2 decoder application that is partitioned and mapped onto two processing elements connected by FIFO buffers.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133216042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

System-level mitigation of WID leakage power variability using body-bias islands 使用体偏置岛的WID泄漏功率变异性的系统级缓解

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450197

S. Garg, Diana Marculescu

{"title":"System-level mitigation of WID leakage power variability using body-bias islands","authors":"S. Garg, Diana Marculescu","doi":"10.1145/1450135.1450197","DOIUrl":"https://doi.org/10.1145/1450135.1450197","url":null,"abstract":"Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of \"body-bias islands,\" each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131444874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design 多处理器片上系统协同设计的并发仿真与并行应用分析

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450138

G. Beltrame, L. Fossati, D. Sciuto

引用次数: 4

Design and defect tolerance beyond CMOS 超越CMOS的设计和缺陷容忍度

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450187

X. Hu, A. Khitun, K. Likharev, M. Niemier, M. Bao, Kang L. Wang

{"title":"Design and defect tolerance beyond CMOS","authors":"X. Hu, A. Khitun, K. Likharev, M. Niemier, M. Bao, Kang L. Wang","doi":"10.1145/1450135.1450187","DOIUrl":"https://doi.org/10.1145/1450135.1450187","url":null,"abstract":"It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement/replacement to CMOS must show significant gains in at least one of the key metrics (including speed, power and cost) for at least a subset of application domains currently employing CMOS circuits. In addition, effective defect tolerant techniques are a critical factor for the successful adoption of any new computing device due to the fact that nano-scale structures will have defect rates much higher than today's CMOS chips. The task of identifying application domains that could benefit the most from a new model/device/technology and ensuring that the resultant system meets functional requirements in the presence of defects requires synergistic efforts of physical scientists, and circuit and system design researchers.\u0000 This paper contains a collection of three contributions-each focusing on one particular emergent technology-presenting a basic introduction on the technologies, some of their unique features in contrast with CMOS, potential application domains for these technologies, and new opportunities that they may bring forward in defect tolerance design. The contributions include both traditional and nontraditional state representations which use either electronic or magnetic interactions.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Distributed and low-power synchronization architecture for embedded multiprocessors 嵌入式多处理器的分布式低功耗同步体系结构

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2008-10-19 DOI: 10.1145/1450135.1450153

Chenjie Yu, Peter Petrov

引用次数: 9

Fast Co-Simulation of Transformative Systems with OS Support 具有操作系统支持的变型系统的快速联合仿真

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2004-09-08 DOI: 10.1109/CODES+ISSS.2004.28

Zhengting He, A. Mok

{"title":"Fast Co-Simulation of Transformative Systems with OS Support","authors":"Zhengting He, A. Mok","doi":"10.1109/CODES+ISSS.2004.28","DOIUrl":"https://doi.org/10.1109/CODES+ISSS.2004.28","url":null,"abstract":"Transformative applications are a class of dataflow computation characterized by iterative behavior. The problem of partitioning a transformative application specification to a set of available hardware (HW) and software (SW) processing elements (PEs) and derivation of a job execution order (scheduling) on them has been quite well studied, but the problem of obtaining fast simulation of these applications poses different constraints. In this paper, we propose an efficient framework for a symmetric multi-processor (SMP) simulation host to achieve fast HW/SW co-simulation for transformative applications, given the partition solutions and the derived schedulers. The framework overcomes the limitations in existing Linux SMP kernel and requires only a reasonable amount of modifications to it. We also present a heuristic algorithm which effectively assigns simulation tasks to the processors on the simulation host, considering both average job simulation time on each processor and other simulation overhead. Our experiments show that the algorithm is able to find satisfactory suboptimal solutions with very little computation time. Based on the task assignment solution, the simulation time can be reduced by 25% to 50% from the obvious but naive approach.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115340643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Embedded systems education: how to teach the required skills? 嵌入式系统教育:如何教授所需的技能?

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016781

P. Marwedel, D. Gajski, Erwin De Kock, Hugo De Man, M. Sami, I. Söderquist

引用次数: 7

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis 从粗粒度数据流规范进行硬件合成，实现快速硬件/软件协同合成

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016730

Hyunuk Jung, S. Ha

引用次数: 1

Cellular Handset Technology System Requirements and Integration Trends 蜂窝手机技术系统需求与集成趋势

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2004-09-08 DOI: 10.1109/CODES+ISSS.2004.10

S. Mattisson

引用次数: 0

Architectural versus physical solutions for on-chip communication challenges 芯片上通信挑战的体系结构与物理解决方案

International Conference on Hardware/Software Codesign and System Synthesis Pub Date : 2003-10-01 DOI: 10.1145/944645.944665

D. Burger

{"title":"Architectural versus physical solutions for on-chip communication challenges","authors":"D. Burger","doi":"10.1145/944645.944665","DOIUrl":"https://doi.org/10.1145/944645.944665","url":null,"abstract":"The growing gap between transistor and global wire speeds in sub-100 nanometer technologies poses numerous challenges to computer architects and circuit designers. This challenge looks to be even more significant in far-future technologies such as molecular-scale wire transmission, whether using carbon nanotubes or quantum dots. While a fixed design scales as its area decreases with feature size reductions, future designs that use a constant area see rapidly increasing global latencies.Two approaches to address these latencies are (1) to use signaling and design techniques to reduce the actual latencies, and (2) to use architectural innovations to reduce the distance that signals must be propagated in the common case. In this talk, after an overview of the communication latency issue, I describe current research that aims to reduce the average distance communicated for processing and memory system signals. For processor designs, I will describe the Static Placement, Dynamic Issue (SPDI) execution model, which allows the compiler to place dependent instructions near one another, and which is being implemented in the TRIPS processor. I will also describe Non-Uniform Caches Access (NUCA) designs, which attempt to reduce average signal distance for cache accesses.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134309496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0