2019 IEEE International Conference on Rebooting Computing (ICRC)最新文献

Message from the 2019 ICRC Program Co-Chairs 2019年红十字国际委员会项目联合主席致辞

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/icrc.2019.8914714

引用次数: 0

On the Limits of Stochastic Computing 论随机计算的极限

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914706

Florian Neugebauer, I. Polian, J. Hayes

引用次数: 3

Integrated Photonics Architectures for Residue Number System Computations 残数系统计算的集成光子体系结构

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914700

Jiaxin Peng, Y. Alkabani, Shuai Sun, V. Sorger, T. El-Ghazawi

{"title":"Integrated Photonics Architectures for Residue Number System Computations","authors":"Jiaxin Peng, Y. Alkabani, Shuai Sun, V. Sorger, T. El-Ghazawi","doi":"10.1109/ICRC.2019.8914700","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914700","url":null,"abstract":"Residue number system (RNS) can represent large numbers as sets of relatively smaller prime numbers. Architectures for such systems can be inherently parallel, as arithmetic operations on large numbers can then be performed on elements of those sets individually. As RNS arithmetic is based on modulo operations, an RNS computational unit is usually constructed as a network of switches that are controlled to perform a specific computation, giving rise to the processing in network (PIN) paradigm. In this work, we explore using integrated photonics switches to build different high-speed architectures of RNS computational units based on multistage interconnection networks. The inherent parallelism of RNS, as well as very low energy of integrated phontonics are two primary reasons for the promise of this direction. We study the trade-offs between the area and the control complexity of five different architectures. We show that our newly proposed architecture, which is based on arbitrary size Benes (AS-Benes) networks, saves up to 90% of the area and is up to 16 times faster than the other architectures.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114624138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Entangled State Preparation for Non-Binary Quantum Computing 非二进制量子计算的纠缠态制备

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914717

Kaitlin N. Smith, M. Thornton

引用次数: 2

Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks 基于非易失性存储器阵列的量化和抗噪声LSTM神经网络

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914713

Wen Ma, P. Chiu, Won Ho Choi, Minghai Qin, D. Bedau, Martin Lueker-Boden

{"title":"Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks","authors":"Wen Ma, P. Chiu, Won Ho Choi, Minghai Qin, D. Bedau, Martin Lueker-Boden","doi":"10.1109/ICRC.2019.8914713","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914713","url":null,"abstract":"In cloud and edge computing models, it is important that compute devices at the edge be as power efficient as possible. Long short-term memory (LSTM) neural networks have been widely used for natural language processing, time series prediction and many other sequential data tasks. Thus, for these applications there is increasing need for low-power accelerators for LSTM model inference at the edge. In order to reduce power dissipation due to data transfers within inference devices, there has been significant interest in accelerating vector-matrix multiplication (VMM) operations using non-volatile memory (NVM) weight arrays. In NVM array-based hardware, reduced bit-widths also significantly increases the power efficiency. In this paper, we focus on the application of quantization-aware training algorithm to LSTM models, and the benefits these models bring in terms of resilience against both quantization error and analog device noise. We have shown that only 4-bit NVM weights and 4-bit ADC/DACs are needed to produce equivalent LSTM network performance as floating-point baseline. Reasonable levels of ADC quantization noise and weight noise can be naturally tolerated within our NVM-based quantized LSTM network. Benchmark analysis of our proposed LSTM accelerator for inference has shown at least 2.4× better computing efficiency and 40× higher area efficiency than traditional digital approaches (GPU, FPGA, and ASIC). Some other novel approaches based on NVM promise to deliver higher computing efficiency (up to ×4.7) but require larger arrays with potential higher error rates.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116990145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

ICRC 2019 Sponsor 红十字国际委员会2019

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/icrc.2019.8914690

引用次数: 0

Future Computing Systems (FCS) to Support "Understanding" Capability 支持“理解”能力的未来计算系统(FCS)

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914712

R. Beausoleil, T. Vaerenbergh, Kirk M. Bresniker, Catherine E. Graves, Kimberly Keeton, Suhas Kumar, Can Li, D. Milojicic, S. Serebryakov, J. Strachan

{"title":"Future Computing Systems (FCS) to Support \"Understanding\" Capability","authors":"R. Beausoleil, T. Vaerenbergh, Kirk M. Bresniker, Catherine E. Graves, Kimberly Keeton, Suhas Kumar, Can Li, D. Milojicic, S. Serebryakov, J. Strachan","doi":"10.1109/ICRC.2019.8914712","DOIUrl":"https://doi.org/10.1109/ICRC.2019.8914712","url":null,"abstract":"The massive explosion in data acquisition, processing, and archiving, accelerated by the end of Moore's Law, creates a challenge and an opportunity for a complete redesign of technology, devices, hardware architecture, software stack and AI stack to enable future computing systems with \"understanding\" capability. We propose a Future Computing System (FCS) based on a memory driven computing AI architecture, that leverages different types of next generation accelerators (e.g., Ising and Hopfield Machines), connected over an intelligent successor of the Gen-Z interconnect. On top of this architecture we propose a software stack and subsequently, an AI stack built on top of the software stack. While intelligence characteristics (learning, training, self-awareness, etc.) permeate all layers, we also separate AI-specific components into a separate layer for clear design. There are two aspects of AI in FCSs: a) AI embedded in the system to make the system better: better performing, more robust, self-healing, maintainable, repairable, and energy efficient. b) AI as the level of reasoning over the information contained within the system: the supervised and unsupervised techniques finding relationships over the data placed into the system. Developing the software and AI stack will require adapting to each redundant component. At least initially, specialization will be required. For this reason, starting with an interoperable, memory driven computing architecture and associated interconnect is essential for subsequent generalization. Our architecture is composable, i.e., it could be pursued in: a) its entirety, b) per-layer c) per component inside of the layer (e.g., only one of the accelerators, use cases, etc.); or d) exploring specific characteristics across the layers.","PeriodicalId":297574,"journal":{"name":"2019 IEEE International Conference on Rebooting Computing (ICRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127584222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Experimental Insights from the Rogues Gallery 来自Rogues画廊的实验见解

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914707

Jeffrey S. Young, E. J. Riedy, T. Conte, Vivek Sarkar, Prasanth Chatarasi, S. Srikanth

引用次数: 11

ICRC 2019 Technical Program 红十字国际委员会2019年技术方案

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/icrc.2019.8914695

Sachin S. Bhat, Csaba Andras, Moritz, M. Inuiguchi, Hirosato, Seki, S. Serebryakov, D. Milojicic, Natalia, Vassilieva, S. Fleischman, D. Bedau, Craig Warner, C. Brueggen, Charles, Williams, Nathaniel Jansen, J. Strachan, Amit, Sharma

引用次数: 0

Design of a 16-Bit Adiabatic Microprocessor 16位绝热微处理器的设计

2019 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2019-11-01 DOI: 10.1109/ICRC.2019.8914699

Rene Celis-Cordova, A. Orlov, Tian Lu, J. Kulick, G. Snider

引用次数: 7