Design of a 16-Bit Adiabatic Microprocessor

Abstract

Heat production is one of the main limiting factors in modern computing. In this paper, we explore adiabatic reversible logic which can dramatically reduce energy dissipation and is a viable implementation of future energy-efficient computing. We present a 16-bit adiabatic microprocessor with a multicycle MIPS architecture designed in 90nm technology. The adiabatic circuits are implemented using split-rail charge recovery logic, which allows the same circuit to be operated both in adiabatic mode and in standard CMOS mode. Simulations of a shift register show that energy dissipation can be much lower when operating in adiabatic mode compared to its CMOS counterpart. We present a standard cell library with all the necessary components to build adiabatic circuits and implement the subsystems of the microprocessor. The microprocessor has a proposed operating frequency of 0.5 GHz representing a useful implementation of adiabatic reversible computing.