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Proceedings 31st IEEE International Symposium on Multiple-Valued Logic最新文献

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Many valued paraconsistent logic 许多有价值的副一致逻辑
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924583
C. Morgan
{"title":"Many valued paraconsistent logic","authors":"C. Morgan","doi":"10.1109/ISMVL.2001.924583","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924583","url":null,"abstract":"In contrast to most logics, in paraconsistent logic it is not true that everything followed from a contradiction. The semantics for one of the best known paraconsistent logics, LP, permits sentences to be both true and false; but at the same time, the semantic characterization of the logical particles is classical. We define the notion of \"molecular logic\", of which all finite valued variants of LP are a type. Generally paraconsistent logics do not contain extensional conditionals. Molecular logics of n values may be conservatively extended to standard many valued logics of 2/sup n/-1 values, in which it is easy to define extensional conditionals with the usual detachment rules. The extension, while paraconsistent relative to a negation satisfying standard conditions on the original n values, is not paraconsistent relative to a negation satisfying standard conditions on the 2/sup n/-1 values of the extension. We conclude that the logic LP and its many valued generalizations are paraconsistent because of expressive incompleteness.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124835890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The use of arithmetic operators in a self-restored current mode CMOS multiple-valued logic design architecture 算术运算符在自恢复电流模式CMOS多值逻辑设计架构中的应用
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924561
H. Teng, R. Bolton
{"title":"The use of arithmetic operators in a self-restored current mode CMOS multiple-valued logic design architecture","authors":"H. Teng, R. Bolton","doi":"10.1109/ISMVL.2001.924561","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924561","url":null,"abstract":"This paper discusses the usage of arithmetic sum and diff operators in a self-restored architecture for current-mode CMOS Multiple-Valued Logic (MVL) design. The self-restored architecture consists of an input block, a control block and an output block. The arithmetic operators can be used in the input block and output block separately or in combination. The average circuit size of certain MVL functions can be reduced significantly.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115526264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On axiomatic characterization of fuzzy approximation operators. II. The rough fuzzy set based case 模糊逼近算子的公理化表征。2基于粗糙模糊集的情况
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924592
H. Thiele
{"title":"On axiomatic characterization of fuzzy approximation operators. II. The rough fuzzy set based case","authors":"H. Thiele","doi":"10.1109/ISMVL.2001.924592","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924592","url":null,"abstract":"In two previous papers we have developed axiomatic characterizations of approximation operators which are defined by the classical diamond and box operator of the modal logic on the one hand and are defined by the \"fuzzified\" diamond and box operator in applying to crisp sets, i.e. by using the concept of fuzzy rough sets on the other hand. The paper presented is a continuation of the first paper mentioned above by applying the classical diamond and box operators to fuzzy sets, i.e. by using the concepts of rough fuzzy sets.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122389861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Information theory method for flexible network synthesis
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924573
V. Cheushev, S. Yanushkevich, V. Shmerko, C. Moraga, J. Kolodziejczyk
{"title":"Information theory method for flexible network synthesis","authors":"V. Cheushev, S. Yanushkevich, V. Shmerko, C. Moraga, J. Kolodziejczyk","doi":"10.1109/ISMVL.2001.924573","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924573","url":null,"abstract":"We introduce a novel approach to extend flexibility of combinational multi-level networks synthesis based on information-theoretical measure (ITM). This problem is related to optimization for combinational multi-level networks, artificial evolution and machine learning in circuitry design. Using ITMs, we verify not only that an evolved network achieves the target functionality, but also that this network can be corrected in a simple regular way to achieve it. We demonstrate experimental results by evolutionary strategy on gate-level network design: effectiveness in evolved valid networks increases dozens of times.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130156126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Tutorial: Complexity of many-valued logics 教程:多值逻辑的复杂性
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924565
Reiner Hähnle
{"title":"Tutorial: Complexity of many-valued logics","authors":"Reiner Hähnle","doi":"10.1109/ISMVL.2001.924565","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924565","url":null,"abstract":"Like in the case of classical logic and other non-standard logics, a variety of complexity-related questions can be asked in the context of many-valued logic. Some questions, such as the complexity of the sets of satisfiable and valid formulas in various logics, are completely standard; others, such as the maximal size of representations of many-valued connectives, only make sense in a many-valued context. In this overview I concentrate mainly on two kinds of complexity problems related to many-valued logics: I discuss the complexity of the membership problem in various languages, such as the satisfiable, respectively, the valid formulas in some well-known logics. Two basic proof techniques an presented in some detail: a reduction of many-valued logic to mixed integer programming and a reduction to classical logic.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Identification of incompletely specified fuzzy unate logic function 不完全指定模糊单值逻辑函数的辨识
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924563
H. Kikuchi
{"title":"Identification of incompletely specified fuzzy unate logic function","authors":"H. Kikuchi","doi":"10.1109/ISMVL.2001.924563","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924563","url":null,"abstract":"Fuzzy logic function f is unate if and only if f is either monotone increasing or monotone decreasing with regards to every variable. This paper studies some fundamental properties of fuzzy unate logic function. Based on the properties, this paper clarifies a necessary and sufficient condition of any given incompletely specified function to be unate fuzzy logic function.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121988335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Decomposition of multi-valued functions into min- and max-gates 多值函数分解为极小门和极大门
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924569
C. Lang, B. Steinbach
{"title":"Decomposition of multi-valued functions into min- and max-gates","authors":"C. Lang, B. Steinbach","doi":"10.1109/ISMVL.2001.924569","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924569","url":null,"abstract":"This paper presents algorithms that allow the realization of multi-valued functions as a multi-level network consisting of min- and max-gates. The algorithms are based on bi-decomposition of function intervals, a generalization of incompletely specified functions. Multi-valued derivation operators are applied to compute decomposition structures. For validation the algorithms have been implemented in the YADE system. Results of the decomposition of functions from machine learning applications are listed and compared to the results of another decomposer.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Cut-elimination in a sequents-of-relations calculus for Godel logic 哥德尔逻辑的关系序列演算中的切消
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924570
M. Baaz, A. Ciabattoni, C. Fermüller
{"title":"Cut-elimination in a sequents-of-relations calculus for Godel logic","authors":"M. Baaz, A. Ciabattoni, C. Fermüller","doi":"10.1109/ISMVL.2001.924570","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924570","url":null,"abstract":"Previously, the analytic calculus RG/sub /spl infin// for Godel logic has been introduced. RG/sub /spl infin// operates on \"sequents of relations\". We show constructively how to eliminate cuts from RG/sub /spl infin//-derivations. The version of the cut rule we consider allows to derive other forms of cut as well as a rule corresponding to the \"communication rule\" of Avron's hypersequent calculus for G/sub /spl infin//. Moreover, we give an explicit description of all the axioms of RG/sub /spl infin// and prove their completeness.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117030410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Synthesis of multiple-valued arithmetic circuits using evolutionary graph generation 基于进化图生成的多值算术电路综合
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924581
M. Natsui, T. Aoki, T. Higuchi
{"title":"Synthesis of multiple-valued arithmetic circuits using evolutionary graph generation","authors":"M. Natsui, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.2001.924581","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924581","url":null,"abstract":"This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the transistor-level design of multiple-valued arithmetic circuits. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The potential capability of EGG is demonstrated through an experimental synthesis of a radix-4 signed-digit full adder circuit.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126751896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A functional manipulation for improving tolerance against multiple-valued weight faults of feedforward neural networks 一种提高前馈神经网络对多值权错误容忍度的功能操作
Proceedings 31st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2001-05-22 DOI: 10.1109/ISMVL.2001.924593
N. Kamiura, Yasuyuki Taniguchi, N. Matsui
{"title":"A functional manipulation for improving tolerance against multiple-valued weight faults of feedforward neural networks","authors":"N. Kamiura, Yasuyuki Taniguchi, N. Matsui","doi":"10.1109/ISMVL.2001.924593","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924593","url":null,"abstract":"In this paper we propose feedforward neural networks (NNs for short) tolerating multiple-valued stuck-at faults of connection weights. To improve the fault tolerance against faults with small false absolute values, we employ the activation function with the relatively gentle gradient for the last layer, and steepen the gradient of the function in the intermediate layer. For faults with large false absolute values, the function working as filter inhibits their influence by setting products of inputs and faulty weights to allowable values. The experimental results show that our NN is superior in fault tolerance and learning time to other NNs employing approaches based on fault injection, forcible weight limit and so forth.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126073268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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