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Proceedings European Design and Test Conference. ED & TC 97最新文献

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The input pattern fault model and its application 输入模式故障模型及其应用
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582441
R. D. Blanton, J. Hayes
{"title":"The input pattern fault model and its application","authors":"R. D. Blanton, J. Hayes","doi":"10.1109/EDTC.1997.582441","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582441","url":null,"abstract":"The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit primitive, independent of the design level. Here, we formalize the model and provide a method for analyzing IP faults using single stuck-line (SSL) based tools.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Two-way partitioning based on direction vector [layout design] 基于方向矢量的双向划分[布局设计]
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582375
K. Seong, C. Kyung
{"title":"Two-way partitioning based on direction vector [layout design]","authors":"K. Seong, C. Kyung","doi":"10.1109/EDTC.1997.582375","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582375","url":null,"abstract":"In the spectral method, the vertices in a graph can be mapped into the vectors in d-dimensional space, thus the vectors are partitioned instead of vertices to obtain graph partitioning. In this paper, we show a method to obtain optimal two-way vector partitioning based on an optimal direction vector. As the problem to find the optimal direction vector is NP-problem, we propose an efficient heuristic to obtain high quality direction vector. As we approximate a given netlist into the graph and only use ten eigenvectors in practice, there is a chance to improve the solution quality by local optimization. Fiduccia-Mattheyses algorithm is employed as a post processing. Compared with FM and MELO, the proposed algorithm PDV reduces cutsize on the average 40% and 20.5%, respectively.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133898745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits MOSAIC:一个多策略导向的顺序ATPG集成电路
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582326
A. Dargelas, C. Gauthron, Y. Bertrand
{"title":"MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits","authors":"A. Dargelas, C. Gauthron, Y. Bertrand","doi":"10.1109/EDTC.1997.582326","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582326","url":null,"abstract":"The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of algorithms in several passes to detect faults. Our so-called Multiple Strategy Approach takes into account the existing techniques and algorithms, (improvements are proposed for some of them) and at each step selects the strategy that is best adapted to catch the targeted faults. This work has been done with a focus on designing a real industrial ATPG, able to handle real circuits consisting of several hundreds of thousands of gates.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130026847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Reconfigurable data converter as a building block for mixed-signal test 可重构数据转换器作为混合信号测试的构建块
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582383
Edward K. F. Lee
{"title":"Reconfigurable data converter as a building block for mixed-signal test","authors":"Edward K. F. Lee","doi":"10.1109/EDTC.1997.582383","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582383","url":null,"abstract":"A reconfigurable data converter (RDC) that can be configured to a number of ADCs and DACs having different speeds and resolutions for testing mixed-signal systems is proposed. It can be used as a building block in mixed-signal boundary scan or built-in self-test (BIST) techniques. The RDC can also be configured as random noise generators and used as test stimuli in BIST. Since the required area of the proposed RDC is only slightly larger than that of a conventional pipelined ADC, it can be used in many mixed-signal systems.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Delay management for programmable video signal processors 可编程视频信号处理器的延迟管理
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582345
M. L. G. Smeets, E. Aarts, G. Essink, E. Kock
{"title":"Delay management for programmable video signal processors","authors":"M. L. G. Smeets, E. Aarts, G. Essink, E. Kock","doi":"10.1109/EDTC.1997.582345","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582345","url":null,"abstract":"We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"39 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and verification of the sequential systems automata using temporal logic specifications 使用时序逻辑规范设计和验证时序系统自动机
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582436
Anatol Ursu, Gabriela Gruita, S. Zaporojan
{"title":"Design and verification of the sequential systems automata using temporal logic specifications","authors":"Anatol Ursu, Gabriela Gruita, S. Zaporojan","doi":"10.1109/EDTC.1997.582436","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582436","url":null,"abstract":"A design and verification method of sequential systems automata using temporal logic specifications is proposed. The method is based on well-known Z. Manna and P. Wolper temporal logic satisfiability analysis procedure. A new satisfiability analysis algorithm for temporal logic specifications which includes past time as well as future time temporal logic operators is proposed. A case study is carried out which deals with two design examples.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126642562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors 异构多处理机上多速率系统的分层调度与分配
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582347
Yanbing Li, W. Wolf
{"title":"Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors","authors":"Yanbing Li, W. Wolf","doi":"10.1109/EDTC.1997.582347","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582347","url":null,"abstract":"This paper describes new algorithms for system-level software synthesis, namely the scheduling and allocation of a set of complex tasks running at multiple rates on a heterogeneous multiprocessor. The tasks may have precedence constraints within them. The multiprocessor may be composed of both programmable and fixed-function processing elements and may have arbitrary interconnect topology. Our hierarchical algorithm takes advantage of the hierarchical structure of the system's task graph to hierarchically allocate and schedule processes on the multiprocessor to meet the hard real-time constraints on the tasks. Multimedia is an important application of our algorithm.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121130201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications 高速电信应用中多速率和可变速率电路的合成
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582414
P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, I. Bolsens
{"title":"Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications","authors":"P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, I. Bolsens","doi":"10.1109/EDTC.1997.582414","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582414","url":null,"abstract":"A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modern design from the link level to the gate level. The methodology uses a C++-based untimed dataflow system description, which is gradually refined to an optimized, bit-true and clock cycle true C++-description. Through this refinement, a bridge from link level design semantics to architectural VHDL semantics is made within one and the same environment.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121291315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel methodology for designing TSC networks based on the parity bit code 一种基于奇偶位码的TSC网络设计方法
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582397
C. Bolchini, F. Salice, D. Sciuto
{"title":"A novel methodology for designing TSC networks based on the parity bit code","authors":"C. Bolchini, F. Salice, D. Sciuto","doi":"10.1109/EDTC.1997.582397","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582397","url":null,"abstract":"Combinational circuits encoded with the parity bit code can be defined TSC if and only if the number of the observed outputs modified by any admissible fault (fault observability) is odd. The methodology presented in this paper allows the use of the parity bit code by synthesizing an encoded network and then modifying the observability of each fault f/spl isin/F by introducing an auxiliary output, if necessary. In particular, the function implementing the auxiliary output allows an odd observability every time the observability of an internal node in the initial realization is even.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126973605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Register synthesis for speculative computation 用于推测计算的寄存器综合
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582401
D. Herrmann, R. Ernst
{"title":"Register synthesis for speculative computation","authors":"D. Herrmann, R. Ernst","doi":"10.1109/EDTC.1997.582401","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582401","url":null,"abstract":"Speculative computation and branch prediction have been used in high-performance processor design for many years. Recently it has also been applied to high-level synthesis where a priori knowledge of possible control paths provides an even higher performance potential. One problem of speculative techniques is the circuit overhead necessary for correctness preservation. While in processors, overhead is high due to the required generality, high-level synthesis can, again, employ a priori knowledge. The paper presents a register synthesis and allocation technique for speculative computation with branch prediction which is based on life time trees. It creates shift register structures with little register and control overhead.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130200698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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