Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications

A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modern design from the link level to the gate level. The methodology uses a C++-based untimed dataflow system description, which is gradually refined to an optimized, bit-true and clock cycle true C++-description. Through this refinement, a bridge from link level design semantics to architectural VHDL semantics is made within one and the same environment.