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Proceedings European Design and Test Conference. ED & TC 97最新文献

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Microsystem design using simulator coupling 采用模拟器耦合的微系统设计
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582342
S. Wünsche, C. Clauß, P. Schwarz, F. Winkler
{"title":"Microsystem design using simulator coupling","authors":"S. Wünsche, C. Clauß, P. Schwarz, F. Winkler","doi":"10.1109/EDTC.1997.582342","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582342","url":null,"abstract":"The microsystem design process is characterized by interdisciplinary approaches and close interactions between different domains. A methodology for simulating the performance of complex microsystems using simulator coupling is presented. The technique is based on the coupling of the FEM program ANSYS with the circuit and system simulator SABER. In difference to other known simulator couplings a time step algorithm is employed. Its methodology is reported and the implementation into simulation tools is explained. The system simulations of an acceleration sensor system as well as the simulation of thermal interactions in integrated circuits prove the suitability of the coupling. Finally simulation results are discussed and advantages of the implemented coupling are concluded.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High-level synthesis of analog sensor interface front-ends 模拟传感器接口前端的高级综合
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582330
S. Donnay, G. Gielen, W. Sansen, W. Kruiskamp, D. Leenaerts, W. V. Bokhoven
{"title":"High-level synthesis of analog sensor interface front-ends","authors":"S. Donnay, G. Gielen, W. Sansen, W. Kruiskamp, D. Leenaerts, W. V. Bokhoven","doi":"10.1109/EDTC.1997.582330","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582330","url":null,"abstract":"In this paper we compare three different methodologies for analog high-level synthesis. Two optimization-based methods-one with simulations in the loop, the other with equations-and a library-based approach are discussed and illustrated with experimental results. The comparison is made by means of a real life design example-a radiation detector interface ASIC-although the methodologies presented in this paper, are generally applicable.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132596273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems RATAN:用于嵌入式系统的速率分析和速率约束调试的工具
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582322
Ali Dasdan, Anmol Mathur, Rajesh K. Gupta
{"title":"RATAN: A tool for rate analysis and rate constraint debugging for embedded systems","authors":"Ali Dasdan, Anmol Mathur, Rajesh K. Gupta","doi":"10.1109/EDTC.1997.582322","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582322","url":null,"abstract":"The increasingly complex design of embedded systems creates the problems of specifying consistent and satisfiable rate constraints on process execution rates, checking them for consistency and satisfiability, computing process execution rates, and debugging rate constraint violations. The high complexity of these problems requires a complete and automated framework to help the designer in producing correct systems in shorter design time. We present such a framework and its implementation in a tool called Ratan. Experiments on large benchmarks show the suitability of the tool for an interactive debugging environment.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131225111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language 用模拟硬件描述语言对微系统中机电换能器进行建模和仿真
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582344
B. Romanowicz, M. Laudon, P. Lerch, P. Renaud, H. Amann, A. Boegli, Vincent Moser, F. Pellandini
{"title":"Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language","authors":"B. Romanowicz, M. Laudon, P. Lerch, P. Renaud, H. Amann, A. Boegli, Vincent Moser, F. Pellandini","doi":"10.1109/EDTC.1997.582344","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582344","url":null,"abstract":"The analytical modeling and simulation of conservative electrostatic, electromagnetic and electrodynamic transducers found in microsystems using a non-linear lumped-parameter approach is presented in this paper. A comparison is made between this approach and the linearized equivalent circuit method. All models of transducers are written in HDL-A/sup TM/, a proprietary analogue hardware description language (HDL). System-level simulation is performed in the SPICE simulator using behavioral models of the transducers. Finally, a parameter extraction and HDL model generation tool for devices is presented.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131139719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Accurate high level datapath power estimation 准确的高层次数据路径功率估计
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582421
Jim E. Crenshaw, M. Sarrafzadeh
{"title":"Accurate high level datapath power estimation","authors":"Jim E. Crenshaw, M. Sarrafzadeh","doi":"10.1109/EDTC.1997.582421","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582421","url":null,"abstract":"The cubic switching table is a new data structure for estimating datapath switching at a high level. It is constructed during behavioral simulation, and is used to estimate the switching for any particular datapath schedule and binding. Time to extract the estimate from the table is independent of the original simulation size. For n operations in the RTL description, it takes O(n/sup 3/) time to perform the extraction. We show that an exact switching table would require exponential size, but experimental results show that the cubic table is accurate, with typical error under 5%.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123188257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model 可变延迟模型下组合CMOS电路的加权开关活动最大化
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582422
S. Manich, J. Figueras
{"title":"Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model","authors":"S. Manich, J. Figueras","doi":"10.1109/EDTC.1997.582422","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582422","url":null,"abstract":"A methodology to find the couple of vectors maximizing the weighted switching activity in combinational CMOS circuits under variable delay model is presented. The weighted switching activity maximization problem is shown to be equivalent to a fault testing problem on a transformed circuit. A maximum weighted switching activity is achieved by test vectors covering a selected set of faults of the transformed circuit. Automatic Test and Pattern Generation tools are used to find the maximizing pair of vectors. The validity of the proposal is demonstrated on the ISCAS-85 benchmark circuits and the results show that the simulation time is reduced by an order of magnitude and the estimation of the maximum weighted switching activity is improved in comparison with pseudo-random sample simulation.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123623176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Minimizing ROBDD sizes of incompletely specified Boolean functions by exploiting strong symmetries 利用强对称性最小化不完全指定布尔函数的ROBDD大小
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582364
Christoph Scholl, S. Melchior, G. Hotz, P. Molitor
{"title":"Minimizing ROBDD sizes of incompletely specified Boolean functions by exploiting strong symmetries","authors":"Christoph Scholl, S. Melchior, G. Hotz, P. Molitor","doi":"10.1109/EDTC.1997.582364","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582364","url":null,"abstract":"We present a method computing a minimum sized partition of the variables of an incompletely specified Boolean function into symmetric groups. The method can be used during minimization of ROBDDs of incompletely specified Boolean functions. We apply it as a preprocessing step of symmetric sifting presented by Panda (1994) and Moller (1994) and of techniques for ROBDD minimization of incompletely specified Boolean functions presented by Chang (1994) and Shiple (1994). The technique is shown to be very effective: it improves ROBDD sizes of symmetric sifting by a factor of 51% and by a factor of 70% in combination with a slightly modified version of the technique of Chang and Shiple.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129066507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Multidimensional periodic scheduling: a solution approach 多维周期调度:一种解决方法
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582402
W. Verhaegh, P. Lippens, E. Aarts, J. V. Meerbergen
{"title":"Multidimensional periodic scheduling: a solution approach","authors":"W. Verhaegh, P. Lippens, E. Aarts, J. V. Meerbergen","doi":"10.1109/EDTC.1997.582402","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582402","url":null,"abstract":"We present a solution approach to the multidimensional periodic scheduling problem. We introduce the concept of multidimensional periodic operations in order to cope with problems originating from loop hierarchies and explicit timing requirements. We present an iterative algorithm for the scheduling problem, based on an ILP approach for checking the constraints, and we show some experimental results. Finally, we extend the solution approach to handle parametric descriptions.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
On the use of reset to increase the testability of interconnected finite-state machines 利用复位提高互联有限状态机的可测试性
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582416
I. Pomeranz, S. Reddy
{"title":"On the use of reset to increase the testability of interconnected finite-state machines","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/EDTC.1997.582416","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582416","url":null,"abstract":"We propose a DFT solution for synchronous sequential circuits described as interconnections of finite-state machines, that takes into account specific requirements for justification of test sequences and propagation of fault effects occurring during test generation. We present this solution in the context of the output sequence justification problem. The proposed DFT solution is based on the use of reset. Three types of reset mechanisms are considered, having increasing overhead and increasing flexibility. The third type allows every output sequence over the output alphabet of a machine to be justified.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems 微系统自顶向下设计中参数化有限元模型自动转换为cad布局格式
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582359
M. Lang, D. David, M. Glesner
{"title":"Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems","authors":"M. Lang, D. David, M. Glesner","doi":"10.1109/EDTC.1997.582359","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582359","url":null,"abstract":"A tool for the transfer of solid models used for FEM simulations into different layout formats used by CAD environments is presented. All necessary layers for the fabrication of microcomponents and systems in a given extended commercial CMOS process are generated automatically by this tool. Starting with an acceleration sensor the use of this translator for an application in the top-down design of microsystems with parametric components is described.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123772857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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