{"title":"Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning","authors":"A. Sengupta, N. Chandra, E. R. Kumar","doi":"10.1109/ICCE-Berlin47944.2019.9127238","DOIUrl":"https://doi.org/10.1109/ICCE-Berlin47944.2019.9127238","url":null,"abstract":"Digital signal processing (DSP) and multimedia based reusable Intellectual property (IP) cores form key components of system-on-chips used in consumer electronic devices. They represent years of valuable investment and hence need protection against prevalent threats such as IP cloning and fraudulent claim of ownership. This paper presents a novel crypto digital signature approach which incorporates multiple security modules such as encryption, hashing and encoding for protection of digital signature processing cores. The proposed approach achieves higher robustness (and reliability), in terms of lower probability of coincidence, at lower design cost than existing watermarking approaches for IP cores. The proposed approach achieves stronger proof of authorship (on average by ~39.7%) as well as requires lesser storage hardware compared to a recent similar work.","PeriodicalId":290753,"journal":{"name":"2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114080452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Crypto based Multi-Variable Fingerprinting for Protecting DSP cores","authors":"A. Sengupta, Utkarsha Singh, P. Premchand","doi":"10.1109/ICCE-Berlin47944.2019.9127235","DOIUrl":"https://doi.org/10.1109/ICCE-Berlin47944.2019.9127235","url":null,"abstract":"In the design process of Consumer Electronics (CE) systems, there are several security challenges for a vendor or a buyer to ensure IP rights protection. This paper proposes a novel crypto framework based IP core protection methodology for DSP kernels that embeds a buyer fingerprint into a design during high level synthesis (HLS). The proposed signature encoding for fingerprint is multi-variable in nature offering stronger robustness, low embedding cost and low design overhead. It also makes use of a secure hashing technique to derive the fingerprint signature which provides an added level of security against counterfeiting. Upon testing on standard DSP benchmarks, it was found that the proposed approach satisfies all the major protection features of a fingerprint such as strong robustness to the buyer, low overhead, low run time and low embedding cost. Further with respect to the baseline design (with no fingerprint), the proposed approach offers robustness at 0% design cost overhead. Additionally on comparison with a related work, the proposed approach offers a lesser design cost and lesser area overhead without compromising robustness.","PeriodicalId":290753,"journal":{"name":"2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133977798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic","authors":"Mahendra Rathor, A. Sengupta","doi":"10.1109/ICCE-Berlin47944.2019.9127236","DOIUrl":"https://doi.org/10.1109/ICCE-Berlin47944.2019.9127236","url":null,"abstract":"Due to globalization of Integrated Circuit (IC) design flow, Intellectual Property (IP) cores have increasingly become susceptible to various hardware threats such as Trojan insertion, piracy, overbuilding etc. An IP core can be secured against these threats using functional obfuscation based security mechanism. This paper presents a functional obfuscation of digital signal processing (DSP) core for consumer electronics systems using a novel IP core locking block (ILB) logic that leverages the structure of flip-flops and combinational circuits. These ILBs perform the locking of the functionality of a DSP design and actuate the correct functionality only on application of a valid key sequence. In existing approaches so far, executing exhaustive trials are sufficient to extract the valid keys from an obfuscated design. However, proposed work is capable of hindering the extraction of valid keys even on exhaustive trials, unless successfully applied in the first attempt only. In other words, the proposed work drastically reduces the probability of obtaining valid key of a functionally obfuscated design in exhaustive trials. Experimental results indicate that the proposed approach achieves higher security and lower design overhead than previous works.","PeriodicalId":290753,"journal":{"name":"2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128615896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware Steganography for IP Core Protection of Fault Secured DSP Cores","authors":"A. Sengupta, Gargi Gupta, Harshit Jalan","doi":"10.1109/ICCE-Berlin47944.2019.9127237","DOIUrl":"https://doi.org/10.1109/ICCE-Berlin47944.2019.9127237","url":null,"abstract":"Security of transient fault secured IP cores against piracy, false claim of ownership can be achieved during high level synthesis, especially when handling DSP or multimedia cores. Though watermarking that involves implanting a vendor defined signature onto the design can be useful, however research has shown its limitations such as less designer control, high overhead due to extreme dependency on signature size, combination and encoding rule. This paper proposes an alternative paradigm called ‘hardware steganography’ where hidden additional designer’s constraints are implanted in a fault secured IP core using entropy thresholding. In proposed hardware steganography, concealed information in the form of additional edges having a specific entropy value is embedded in the colored interval graph (CIG). This is a signature free approach and ensures high designer control (more robustness and stronger proof of authorship) as well as lower overhead than watermarking schemes used for DSP based IP cores.","PeriodicalId":290753,"journal":{"name":"2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133892766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}