Hardware Steganography for IP Core Protection of Fault Secured DSP Cores

Abstract

Security of transient fault secured IP cores against piracy, false claim of ownership can be achieved during high level synthesis, especially when handling DSP or multimedia cores. Though watermarking that involves implanting a vendor defined signature onto the design can be useful, however research has shown its limitations such as less designer control, high overhead due to extreme dependency on signature size, combination and encoding rule. This paper proposes an alternative paradigm called ‘hardware steganography’ where hidden additional designer’s constraints are implanted in a fault secured IP core using entropy thresholding. In proposed hardware steganography, concealed information in the form of additional edges having a specific entropy value is embedded in the colored interval graph (CIG). This is a signature free approach and ensures high designer control (more robustness and stronger proof of authorship) as well as lower overhead than watermarking schemes used for DSP based IP cores.