2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第7页

Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks 利用铁电晶体管加速深度神经网络的三元计算存储器

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116495

S. Thirumala, Shubham Jain, S. Gupta, A. Raghunathan

{"title":"Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks","authors":"S. Thirumala, Shubham Jain, S. Gupta, A. Raghunathan","doi":"10.23919/DATE48585.2020.9116495","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116495","url":null,"abstract":"Ternary Deep Neural Networks (DNNs), which employ ternary precision for weights and activations, have recently been shown to attain accuracies close to full-precision DNNs, raising interest in their efficient hardware realization. In this work we propose a Non-Volatile Ternary Compute-Enabled memory cell (TeC-Cell) based on ferroelectric transistors (FEFETs) for inmemory computing in the signed ternary regime. In particular, the proposed cell enables storage of ternary weights and employs multi-word-line assertion to perform massively parallel signed dot-product computations between ternary weights and ternary inputs. We evaluate the proposed design at the array level and show 72% and 74% higher energy efficiency for multiply-andaccumulate (MAC) operations compared to standard nearmemory computing designs based on SRAM and FEFET, respectively. Furthermore, we evaluate the proposed TeC-Cell in an existing ternary in-memory DNN accelerator. Our results show 3.3X-3.4X reduction in system energy and 4.3X-7X improvement in system performance over SRAM and FEFET based nearmemory accelerators, across a wide range of DNN benchmarks including both deep convolutional and recurrent neural networks.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116858538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes MiniDelay:先进技术节点的多策略时间感知层分配

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116269

Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang

{"title":"MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes","authors":"Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang","doi":"10.23919/DATE48585.2020.9116269","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116269","url":null,"abstract":"Layer assignment, a major step in global routing of integrated circuits, is usually performed to assign segments of nets to multiple layers. Besides the traditional optimization goals such as overflow and via count, interconnect delay plays an important role in determining chip performance and has been attracting much attention in recent years. Accordingly, in this paper, we propose MiniDelay, a timing-aware layer assignment algorithm to minimize delay for advanced technology nodes, taking both wire congestion and coupling effect into account. MiniDelay consists of the following three key techniques: 1) a non-default-rule routing technique is adopted to reduce the delay of timing critical nets, 2) an effective congestion assessment method is proposed to optimize delay of nets and via count simultaneously, and 3) a net scalpel technique is proposed to further reduce the maximum delay of nets, so that the chip performance can be improved in a global manner. Experimental results on multiple benchmarks confirm that the proposed algorithm leads to lower delay and few vias, while achieving the best solution quality among the existing algorithms with the shortest runtime.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115747573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Optimizing Performance of Persistent Memory File Systems using Virtual Superpages 使用虚拟超页优化持久性内存文件系统的性能

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116411

Chaoshu Yang, Duo Liu, Runyu Zhang, Xianzhang Chen, Shun Nie, Qingfeng Zhuge, E. Sha

{"title":"Optimizing Performance of Persistent Memory File Systems using Virtual Superpages","authors":"Chaoshu Yang, Duo Liu, Runyu Zhang, Xianzhang Chen, Shun Nie, Qingfeng Zhuge, E. Sha","doi":"10.23919/DATE48585.2020.9116411","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116411","url":null,"abstract":"Existing persistent memory file systems can significantly improve the performance by utilizing the advantages of emerging Persistent Memories (PMs). Especially, they can employ superpages (e.g., 2MB a page) of PMs to alleviate the overhead of locating file data and reduce TLB misses. Unfortunately, superpage also induces two critical problems. First, the data consistency of file systems using superpages causes severe write amplification during overwrite of file data. Second, existing management of superpages may lead to large waste of PM space. In this paper, we propose a Virtual Superpage Mechanism (VSM) to solve the problems by taking advantages of virtual address space. On one hand, VSM adopts multi-grained copy-on-write mechanism to reduce the write amplification while ensuring data consistency. On the other hand, VSM presents zero-copy file data migration mechanism to eliminate the loss of space utilization efficiency caused by superpages. We implement the proposed VSM mechanism in Linux kernel based on PMFS. Compared with the original PMFS and NOVA, the experimental results show that VSM improves 36% and 14% on average for write and read performance, respectively. Meanwhile, VSM can achieve the same space utilization efficiency of file system that uses the normal 4KB pages to organize files.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123379572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Multi-Agent Actor-Critic Method for Joint Duty-Cycle and Transmission Power Control 联合占空比与传输功率控制的多智能体actor - critical方法

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116518

Sota Sawaguchi, J. Christmann, A. Molnos, C. Bernier, S. Lesecq

{"title":"Multi-Agent Actor-Critic Method for Joint Duty-Cycle and Transmission Power Control","authors":"Sota Sawaguchi, J. Christmann, A. Molnos, C. Bernier, S. Lesecq","doi":"10.23919/DATE48585.2020.9116518","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116518","url":null,"abstract":"In energy-harvesting Internet of Things (EH-IoT) wireless networks, maintaining energy neutral operation (ENO) is crucial for their perpetual operation and maintenance-free property. Guaranteeing this ENO condition and optimal power-performance trade-off under transient harvested energy and wireless channel quality is particularly challenging. This paper proposes a multi-agent actor-critic reinforcement learning for modulating both the transmitter duty-cycle and output power based on the state-of-buffer (SoB) and the state-of-charge (SoC) information as a state. Thanks to these buffers, differently from the state-of-the-art, our solution does not require any model of the wireless transceiver nor any direct measurement of both harvested energy and wireless channel quality for adapting to these uncertainties. Simulation results of a solar powered EH-IoT node using real-life outdoor solar irradiance data show that the proposed method achieves better performance without system failures throughout a year compared to the state-of-the-art that suffers some system downtime. Our approach also predicts almost no system fails during five years of operation.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122994046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Impact of NBTI Aging on Self-Heating in Nanowire FET NBTI老化对纳米线场效应管自热的影响

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116267

Om. Prakash, H. Amrouch, S. Manhas, J. Henkel

{"title":"Impact of NBTI Aging on Self-Heating in Nanowire FET","authors":"Om. Prakash, H. Amrouch, S. Manhas, J. Henkel","doi":"10.23919/DATE48585.2020.9116267","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116267","url":null,"abstract":"This is the first work that investigates the impact of Negative Bias Temperature Instability (NBTI) on the Self-Heating (SH) phenomenon in Silicon Nanowire Field-Effect Transistors (SiNW-FETs). We investigate the individual as well as joint impact of NBTI and SH on pSiNW-FETs and demonstrate that NBTI-induced traps mitigate SH effects due to reduced current densities. Our Technology CAD (TCAD)-based SiNW-FET device is calibrated against experimental data. It accounts for thermodynamic and hydrodynamic effects in 3-D nano structures for accurate modeling of carrier transport mechanisms. Our analysis focuses on how lattice temperature, thermal resistance and thermal capacitance of pSiNW-FETs are affected due to NBTI, demonstrating that accurate self-heating modeling necessitates considering the effects that NBTI aging has over time. Hence, NBTI and SH effects need to be jointly and not individually modeled. Our evaluation shows that an individual modeling of NBTI and SH effects leads to a noticeable overestimation of the overall induced delay increase in circuits due to the impact of NBTI traps on SH mitigation. Hence, it is necessary to model NBTI and SH effects jointly in order to estimate efficient (i.e. small, yet sufficient) timing guardbands that protect circuits against timing violations, which will occur at runtime due to delay increases induced by aging and self-heating.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121412719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware SOLOMON:一种自动检测硬件故障攻击漏洞的框架

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116380

Milind Srivastava, Patanjali Slpsk, Indrani Roy, C. Rebeiro, Aritra Hazra, S. Bhunia

引用次数: 16

Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections 通过混淆横排连接增强RRAM计算系统的安全性

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116549

Minhui Zou, Zhenhua Zhu, Yi Cai, Junlong Zhou, Chengliang Wang, Yu Wang

{"title":"Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections","authors":"Minhui Zou, Zhenhua Zhu, Yi Cai, Junlong Zhou, Chengliang Wang, Yu Wang","doi":"10.23919/DATE48585.2020.9116549","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116549","url":null,"abstract":"Neural networks (NN) have gained great success in visual object recognition and natural language processing, but this kind of data-intensive applications requires huge data movements between computing units and memory. Emerging resistive random-access memory (RRAM) computing systems have demonstrated great potential in avoiding the huge data movements by performing matrix-vector-multiplications in memory. However, the nonvolatility of the RRAM devices may lead to potential stealing of the NN weights stored in crossbars and the adversary could extract the NN models from the stolen weights. This paper proposes an effective security enhancing method for RRAM computing systems to thwart this sort of piracy attack. We first analyze the theft methods of the NN weights. Then we propose an efficient security enhancing technique based on obfuscating the row connections between positive crossbars and their pairing negative crossbars. Two heuristic techniques are also presented to optimize the hardware overhead of the obfuscation module. Compared with existing NN security work, our method eliminates the additional RRAM writing operations used for encryption/decryption, without shortening the lifetime of RRAM computing systems. The experiment results show that the proposed methods ensure the trial times of brute-force attack are more than (16!)17 and the classification accuracy of the incorrectly extracted NN models is less than 20%, with minimal area overhead.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125224352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

2DCC: Cache Compression in Two Dimensions 二维缓存压缩

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116279

Amin Ghasemazar, M. Ewais, Prashant J. Nair, Mieszko Lis

{"title":"2DCC: Cache Compression in Two Dimensions","authors":"Amin Ghasemazar, M. Ewais, Prashant J. Nair, Mieszko Lis","doi":"10.23919/DATE48585.2020.9116279","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116279","url":null,"abstract":"The importance of caches for performance, and their high silicon area cost, have motivated hardware solutions that transparently compress the cached data to increase effective capacity without sacrificing silicon area. To this end, prior work has taken one of two approaches: either (a) deduplicating identical cache blocks across the cache to take advantage of inter-block redundancy or (b) compressing common patterns within each cache block to take advantage of intra-block redundancy.(p)(/p)In this paper, we demonstrate that leveraging only one of these redundancy types leads to a significant loss in compression opportunities for several applications: some workloads exhibit either inter-block or intra-block redundancy, while others exhibit both. We propose 2DCC (Two Dimensional Cache Compression), a simple technique that takes advantage of both types of redundancy. Across the SPEC and Parsec benchmark suites, 2DCC results in a 2.12× compression factor (geomean) compared to 1.44–1.49× for best prior techniques on an iso-silicon basis. For the cache-sensitive subset of these benchmarks run in isolation, 2DCC also achieves a 11.7% speedup (geomean).","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125224393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Energy Optimization in NCFET-based Processors 基于ncfeet处理器的能量优化

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116301

Sami Salamin, Martin Rapp, H. Amrouch, A. Gerstlauer, J. Henkel

{"title":"Energy Optimization in NCFET-based Processors","authors":"Sami Salamin, Martin Rapp, H. Amrouch, A. Gerstlauer, J. Henkel","doi":"10.23919/DATE48585.2020.9116301","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116301","url":null,"abstract":"Energy consumption is a key optimization goal for all modern processors. Negative Capacitance Field-Effect Transistors (NCFETs) are a leading emerging technology that promises outstanding performance in addition to better energy efficiency. Thickness of the additional ferroelectric layer, frequency, and voltage are the key parameters in NCFET technology that impact the power and frequency of processors. However, their joint impact on energy optimization has not been investigated yet.In this work, we are the first to demonstrate that conventional (i.e., NCFET-unaware) dynamic voltage/frequency scaling (DVFS) techniques to minimize energy are sub-optimal when applied to NCFET-based processors. We further demonstrate that state-of-the-art NCFET-aware voltage scaling for power minimization is also sub-optimal when it comes to energy. This work provides the first NCFET-aware DVFS technique that optimizes the processor's energy through optimal runtime frequency/voltage selection. In NCFETs, energy-optimal frequency and voltage are dependent on the workload and technology parameters. Our NCFET-aware DVFS technique considers these effects to perform optimal voltage/frequency selection at runtime depending on workload characteristics. Results show up to 90 % energy savings compared to conventional DVFS techniques. Compared to state-of-the-art NCFET-aware power management, our technique provides up to 72 % energy savings along with 3.7x higher performance.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126303855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial Functions OSCAR:多项式函数的光学随机计算加速器

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116346

Hassnaa El-Derhalli, S. L. Beux, S. Tahar

{"title":"OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial Functions","authors":"Hassnaa El-Derhalli, S. L. Beux, S. Tahar","doi":"10.23919/DATE48585.2020.9116346","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116346","url":null,"abstract":"Approximate computing allows improving design energy efficiency at the cost of computing accuracy. Stochastic computing is an approximate computing technique, where numbers are represented as probabilities using stochastic bit streams. The serial processing of the bit streams leads to reduced hardware complexity but induces high processing latency. Silicon photonics has the potential to overcome this limitation thanks to high propagation speed of signals and high bandwidth. However, the technology remains costly, which calls for optical accelerators capable to adapt to application-specific requirements. In this paper, we propose a reconfigurable optical accelerator capable to adapt to computing accuracy, energy efficiency, and throughput objectives. The architecture can be configured to execute i) 4th order function for high accuracy processing or ii) 2nd order function for high-energy efficiency or high throughput purposes. Evaluations are carried out using image processing Gamma correction application. Compared to a static architecture for which accuracy is defined at design time, the proposed architecture leads to 36.8% energy overhead but increases the range of reachable accuracy by 65%.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129816371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0