2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献

A Non-invasive Wearable Bioimpedance System to Wirelessly Monitor Bladder Filling 一种无创可穿戴生物阻抗系统无线监测膀胱充盈

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/date48585.2020.9116378

M. Reichmuth, Simone Schürle, M. Magno

引用次数: 11

Study on the Compensation of Silicon Photonics-Based Modulators in DCI Applications 硅光子学调制器在DCI应用中的补偿研究

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116414

Naim Ben-Hamida, A. Abdo, Xueyang Li, Md. Samiul Alam, M. Parvizi, C. D’amours, D. Plant

{"title":"Study on the Compensation of Silicon Photonics-Based Modulators in DCI Applications","authors":"Naim Ben-Hamida, A. Abdo, Xueyang Li, Md. Samiul Alam, M. Parvizi, C. D’amours, D. Plant","doi":"10.23919/DATE48585.2020.9116414","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116414","url":null,"abstract":"For next generation high speed optical coherent systems, digital pre-emphasis filters are essential as they can pre-compensate for the transmitter frequency response and mitigate receiver noise enhancement. However, the downside of using full pre-emphasis to completely pre-compensate for the low bandwidth transmitter is that it increases the signal peak-to-average power ratio (PAPR), thus posing a higher effective number of bits (ENoB) requirement for the digital to analog converter (DAC) and increases optical modulation loss. In this paper, we study the impact of partial pre-emphasis filters on signal PAPR and show how partial pre-emphasis reduces DAC ENoB requirements and MZM modulation loss. Our proposed scheme reduced the DAC ENoB requirement from 5 to 4.5 bits at the same implementation SNR. This enables a lower optical module power through the reduction of DAC and driver amplifier (DA) power. The experimental results, for single-pol case for a partial pre-emphasis filter, showed that the system bandwidth can be extended from 10GHz to 20GHz and tolerate a 6dB loss for a 0.4dBQ penalty factor, and a 0.8dB PAPR reduction.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117156839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication 剖析:内存认证的动态倾斜和分裂树

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116548

Saru Vig, Rohan Juneja, S. Lam

{"title":"DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication","authors":"Saru Vig, Rohan Juneja, S. Lam","doi":"10.23919/DATE48585.2020.9116548","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116548","url":null,"abstract":"Memory integrity trees are widely-used to protect external memories in embedded systems against replay, splicing and spoofing attacks. However, existing methods often result in high-performance overhead that is proportional to the height of the tree. Reducing the height of the integrity tree by increasing its arity, however, leads to frequent overflowing of the counters that are used for encryption in the tree. We will show that increasing the tree arity of a widely-use integrity tree from 2 to 8 can result in over 200% increase in memory authentication overhead for some benchmark applications, despite the reduction in tree height. In this paper, we propose DISSECT, a memory authentication framework which utilizes a dynamic memory integrity tree that can adapt to the memory access patterns of the application by progressively adjusting the tree height and arity in order to significantly reduce performance overhead. This is achieved by 1) initializing an integrity tree structure with the largest arity possible to meet the security requirements, 2) dynamically skewing the tree such that the more frequently accessed memory locations are positioned closer to the tree root (overcomes the tree height problem), and 3) dynamically splitting the tree at nodes with counters that are about to overflow (overcomes the counter overflow problem). Experimental results undertaken using Multi2Sim on benchmarks from SPEC-CPU2006, SPLASH-2, and PARSEC demonstrate the performance benefits of our proposed memory integrity tree.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"64 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120989157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

On the Volume Calculation for Conditional DAG Tasks: Hardness and Algorithms* 条件DAG任务的体积计算:硬度和算法*

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116559

Jinghao Sun, Yaoyao Chi, Tianfei Xu, Lei Cao, Nan Guan, Zhishan Guo, W. Yi

引用次数: 2

Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise 考虑过程变化和噪声的基于记忆电阻的交叉条神经形态计算统计训练

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116244

Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann

引用次数: 33

A Convolutional Result Sharing Approach for Binarized Neural Network Inference 二值化神经网络推理的卷积结果共享方法

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116221

Ya-chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, Chun-Yao Wang

引用次数: 4

Nano-Crossbar based Computing: Lessons Learned and Future Directions 基于纳米交叉棒的计算:经验教训和未来方向

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/date48585.2020.9116566

M. Altun, Ismail Cevik, A. Erten, O. Eksik, M. Stan, C. A. Moritz

{"title":"Nano-Crossbar based Computing: Lessons Learned and Future Directions","authors":"M. Altun, Ismail Cevik, A. Erten, O. Eksik, M. Stan, C. A. Moritz","doi":"10.23919/date48585.2020.9116566","DOIUrl":"https://doi.org/10.23919/date48585.2020.9116566","url":null,"abstract":"In this paper, we first summarize our research activities done through our European Union’s Horizon-2020 project between 2015 and 2019. The project has a goal of developing synthesis and performance optimization techniques for nanocrossbar arrays. For this purpose, different computing models including diode, memristor, FET, and four-terminal switch based models, within different technologies including carbon nanotubes, nanowires, and memristors as well as the CMOS technology have been investigated. Their capabilities to realize logic functions and to tolerate faults have been deeply analyzed. From these experiences, we think that instead of replacing CMOS with a completely new crossbar based technology, developing CMOS compatible crossbar technologies and computing models is a more viable solution to overcome challenges in CMOS miniaturization. At this point, four-terminal switch based arrays, called switching lattices, come forward with their CMOS compatibility feature as well as with their area efficient device and circuit realizations. We have showed that switching lattices can be efficiently implemented using a standard CMOS process to implement logic functions by doing experiments in a 65nm CMOS process. Further in this paper, we make an introduction of realizing memory arrays with switching lattices including ROMs and RAMs. Also we discuss challenges and promises in realizing switching lattices for under 30nm CMOS technologies including FinFET technologies.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127159546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity 硅光子微环谐振器:制造非均匀性下的设计优化

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116201

Asif Mirza, Febin P. Sunny, S. Pasricha, M. Nikdast

{"title":"Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity","authors":"Asif Mirza, Febin P. Sunny, S. Pasricha, M. Nikdast","doi":"10.23919/DATE48585.2020.9116201","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116201","url":null,"abstract":"Microring resonators (MRRs) are very often considered as the primary building block in silicon photonic integrated circuits (PICs). Despite many advantages, MRRs are considerably sensitive to fabrication non-uniformity (a.k.a. fabrication process variations), necessitating the use of power-hungry compensation methods (e.g., thermal tuning) to guarantee their reliable operation. Moreover, the design space of MRRs is complicated and includes several highly correlated design parameters, preventing designers from easily exploring and optimizing the design of MRRs against fabrication process variations (FPVs). In this paper, for the first time, we present a comprehensive design space exploration and optimization of MRRs against FPVs. In particular, we indicate how physical design parameters in MRRs can be optimized during design time to enhance their tolerance to FPVs while also improving the insertion loss and quality factor in such devices. Fabrication results obtained by measuring multiple fabricated MRRs designed using our design optimization solution demonstrate a significant 70% improvement on average in MRRs tolerance to different FPVs. Such improvement indicates the efficiency of our novel design optimization solution in reducing the tuning power required for reliable operation of MRRs.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127461323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Is Register Transfer Level Locking Secure? 寄存器传输级锁定安全吗?

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116261

C. Karfa, Ramanuj Chouksey, C. Pilato, S. Garg, R. Karri

引用次数: 14

Ground Plane Partitioning for Current Recycling of Superconducting Circuits 超导电路电流回收的地平面划分

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2020-03-01 DOI: 10.23919/DATE48585.2020.9116557

N. Katam, Bo Zhang, M. Pedram

{"title":"Ground Plane Partitioning for Current Recycling of Superconducting Circuits","authors":"N. Katam, Bo Zhang, M. Pedram","doi":"10.23919/DATE48585.2020.9116557","DOIUrl":"https://doi.org/10.23919/DATE48585.2020.9116557","url":null,"abstract":"Superconducting single flux quantum (SFQ) technology using Josephson junctions (JJs) is an excellent choice for the computing fabrics of the future. Current recycling is a necessary technique for the implementation of large SFQ circuits with energy-efficiency, where circuit partitions with similar bias current requirements are biased serially. Though this technique has been verified for small scale circuits, it has not been implemented for large circuits as there is no trivial way to partition the circuit into circuit blocks with separate ground planes. The major constraints for partitioning are (1) equal bias current and (2) equal area for all the partitions; (3) minimize the connections between adjacent ground planes with high-cost for non-adjacent planes. For the first time, all these constraints are formulated into a cost function and it is minimized with the gradient descent method. The algorithm takes a circuit netlist and the intended number of partitions as inputs and gives the output as groups of cells belonging to separate ground planes. It minimizes the connections among different ground planes and gives a solution on which the current recycling technique can be implemented. The parameters of cost function have been initialized randomly along with minimizing the dimensions to find the solution quickly. On average, 30% of connections are between non-adjacent ground planes for the given benchmark circuits.","PeriodicalId":289525,"journal":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123593745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4