2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)最新文献_第8页

Control technique for variable speed wind turbine using PI controller 基于PI控制器的变速风力发电机组控制技术

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528578

S. Uma, S. Manikandan

引用次数: 11

Mathematical modelling and speed control of a sensored brushless DC motor using intelligent controller 基于智能控制器的感应式无刷直流电动机数学建模与速度控制

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528495

A. Kiruthika, A. Rajan, P. Rajalakshmi

引用次数: 21

AWES: Adaptive web exploration system based on similar user behavior and multiperspective thinking 敬畏:基于相似用户行为和多角度思维的自适应web探索系统

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528476

A. Koul, A. Bahuguna, A. Singh, A. Pandita, M. K. Pattanshetti, R. Goudar

引用次数: 0

Proficient algorithms for replication attack detection in Wireless Sensor Networks — A survey 无线传感器网络中复制攻击检测的熟练算法综述

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528465

R. Sathish, D. R. Kumar

引用次数: 12

Design of low power sequential circuit using clocked pair shared flip flop 基于时钟对共享触发器的低功耗时序电路设计

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528605

N. Nishanth, B. Sathyabhama

{"title":"Design of low power sequential circuit using clocked pair shared flip flop","authors":"N. Nishanth, B. Sathyabhama","doi":"10.1109/ICE-CCN.2013.6528605","DOIUrl":"https://doi.org/10.1109/ICE-CCN.2013.6528605","url":null,"abstract":"The clock system consisting of clock distribution networks and sequential elements is most power consuming VLSI components. Reductions of flip flop, power consumption have a deep impact on the total power consumption. Since power consumption is a major bottleneck of system performance, the clock load should be reduced to reduce the power consumption. The clock distribution network distributes the clock signal from a common point to all the elements that need it. Since this function is vital to synchronous system, much attention has been given to the characteristics of these clock signal and the electrical networks used in their distribution. In synchronous system clock distribution networks consumes a large amount of total power because of high operation frequency of highest capacitance. An effective way to reduce capacity of clock load is by minimizing number of clocked transistor. In low swing differential capturing flip flop system clock distribution networks consumes a large amount of chip power and there exist a more number of clocked transistor. Hence by a novel approach, clocked paired shared flip flop is used to reduce the number of local clocked transistors.","PeriodicalId":286830,"journal":{"name":"2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116915965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Adding persuasive features in graphical password to increase the capacity of KBAM 在图形密码中增加说服功能，以增加KBAM的容量

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528553

U. Yadav, P. Mohod

引用次数: 17

A high speed real time multi-bin CABAC encoder for ultra high resolution video 用于超高分辨率视频的高速实时多bin CABAC编码器

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528494

P. Jayakrishnan, P. V. A. Lincy, R. Niyas

{"title":"A high speed real time multi-bin CABAC encoder for ultra high resolution video","authors":"P. Jayakrishnan, P. V. A. Lincy, R. Niyas","doi":"10.1109/ICE-CCN.2013.6528494","DOIUrl":"https://doi.org/10.1109/ICE-CCN.2013.6528494","url":null,"abstract":"The demand for better quality pictures, smaller sizes, lower energy consumption, lower cost of appliances has been a fuel for creation of better compression standards and great compression rate. The outstanding compression competence of H.264/AVC is extensively used for video conferencing, online streaming and for HD television. Context Adaptive Binary Arithmetic Coding (CABAC) encoder is a vital part in H.264/AVC (Advanced Video Coding) main and high profiles that provides a real time encoding video of ultra high resolution. CABAC compresses the components in the video signal according to the probability of those elements in a given context. CABAC encoder provides great compression rate over Context-Adaptive Variable Length Coding (CAVLC) baseline entropy encoder. An entropy encoder is a scheme used for lossless compression. A video sequence is a combination of bits which is referred as syntax element. The allocation of bits in various Syntax Elements (SE) [3] is analysed for the reduction in large amount of bit level operations involved and computational complexity involved. An optimised scheme for accessing the contexts and a Binary Arithmetic Encoder (BAE) capable of processing four bits simultaneously is presented. Hence parallelism and throughput is achieved by the means of reduction in syntax and bit level dependency. The proposed fully hardwired encoder is synthesised towards a 90nm CMOS cell library in ASIC flow using Cadence RTL Compiler.","PeriodicalId":286830,"journal":{"name":"2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115583789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fair scheduling approach for Load balancing and Fault tolerant in grid environment 网格环境下负载均衡与容错的公平调度方法

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528540

S. K. Karthikumar, M. Preethi, P. Chitra

引用次数: 6

Modeling and analysis of a SWCNT piezoresistive pressure sensor 单壁碳纳米管压阻式压力传感器的建模与分析

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528544

A. E. Bangera, S. Kulkarni

引用次数: 9

Benchmark evaluation of classification methods for single label learning with R 基于R的单标签学习分类方法的基准评价

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN) Pub Date : 2013-03-25 DOI: 10.1109/ICE-CCN.2013.6528603

P. K. A. Chitra, S. Appavu

引用次数: 2