Design of low power sequential circuit using clocked pair shared flip flop

Abstract

The clock system consisting of clock distribution networks and sequential elements is most power consuming VLSI components. Reductions of flip flop, power consumption have a deep impact on the total power consumption. Since power consumption is a major bottleneck of system performance, the clock load should be reduced to reduce the power consumption. The clock distribution network distributes the clock signal from a common point to all the elements that need it. Since this function is vital to synchronous system, much attention has been given to the characteristics of these clock signal and the electrical networks used in their distribution. In synchronous system clock distribution networks consumes a large amount of total power because of high operation frequency of highest capacitance. An effective way to reduce capacity of clock load is by minimizing number of clocked transistor. In low swing differential capturing flip flop system clock distribution networks consumes a large amount of chip power and there exist a more number of clocked transistor. Hence by a novel approach, clocked paired shared flip flop is used to reduce the number of local clocked transistors.