2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

{"title":"A 87.2%-Efficiency 27.12MHz Current-Mode Wireless Power Receiver with Ramp-Assisted Energy Delivery Controller for Implantable Devices","authors":"Ziyang Luo, Hoi Lee","doi":"10.1109/A-SSCC53895.2021.9634807","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634807","url":null,"abstract":"Wireless power transfer is a widely-adopted approach to recharge batteries in implantable devices. For fast charging and reducing the size of the implanted receiver coil, a wireless power receiver needs to support high input power, PIN, and operate at a high resonance frequency, fres, while providing high power efficiency to avoid tissue overheating. These requirements however have various design tradeoffs. The prior resonant voltage-mode receiver was reported to operate at 13.56MHz for direct battery charging, but it adopted six thick-oxide power FETs and an extra 4.7μH inductor, resulting in large conduction loss and degraded power efficiency [1]. Although the resonant current-mode receiver, RCM-RX, shown in Fig. 1, has a simpler structure with only two power FETs MP and MN, it cannot store large PIN due to the concern of the allowable voltage stress on LV power transistors [2], [3]. While a higher PIN is supported in [4], the RCM-RX uses a total of 9 power FETs for an additional SC converter, impairing the power efficiency and operation frequency. The RCM-RX in [5] can operate at 13.56MHz, but its maximum PIN is limited to a relatively low level of 17.5mW due to its peak-voltage timing detection scheme, PVTD. The PVTD would trigger the charging phase control in the NRth cycle and is strongly dependent on the controller delay, tdelay. As shown in Fig. 1, when tdelay becomes more dominant at a higher frequency and is prolonged due to the use of large-size power FETs for supporting higher PIN, tch would be significantly shortened, degrading the power efficiency of the RX.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125400283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3.1-μW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°C","authors":"Jee-Ho Park, Jung-Hye Hwang, Chang-Ho Shin, Seong-Jin Kim","doi":"10.1109/A-SSCC53895.2021.9634717","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634717","url":null,"abstract":"The temperature compensation for ICs is getting more crucial as the process nodes and circuit performances are advanced. A temperature-sensing core needs to be small enough to locate beside the critical nodes in an IC closely for proper compensation. Also, a highly energy-efficient core with low power consumption is desired to monitor temperature being changed slowly and continuously. The temperature sensors based on RC oscillators have emerged for these area- and energy-efficient solutions thanks to their simple architectures compatible with digital systems [1–4]. They measure the duty ratio of an oscillator clock period which relies on the ratio of the PTAT and CTAT properties of the BJT core, and convert it to temperature in the digital domain. In this paper, we present an ultralow-power small-size BJT-based CMOS temperature sensor with an RC oscillator. The proposed sensor creates a temperature-dependent clock frequency that is easily converted back to temperature without any analog trimming. The comparator offset in the RC oscillator is automatically suppressed by a cap-flipping technique, achieving inaccuracy of $pm 1^{circ}mathrm{C} (3 sigma)$ from $- 40^{circ}mathrm{C}$ to $140^{circ}mathrm{C}$ with 0.025-mm2 area occupation and $3.1- mu mathrm{W}$ power consumption in CMOS 110-nm process.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128433220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS","authors":"Dongin Kim, Seonghwan Cho","doi":"10.1109/A-SSCC53895.2021.9634718","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634718","url":null,"abstract":"Clock frequency of microprocessors must be low enough to ensure error-free operation under supply fluctuation. As having a fixed, low-frequency clock results in sub-par performance, previous works have proposed adaptive clocking (AC) where logic blocks receive reduced clock frequency from the PLL when there is supply droop [1–5]. Unfortunately, there is a couple of issues that limit the performance of the AC. First, previous works employ ACs before the clock buffer and thus do not consider the delay of the clock buffer from the PLL output to the logic blocks that could be up to ten clock cycles at GHz clock frequencies [1]. Due to this delay, the logic block may not receive the correctly adjusted clock when there is supply droop as shown in Fig. 1(a). Second, previous ACs achieve limited performance as the reduced clock frequency is either a fixed or coarsely quantized value [1–4], and does not adapt optimally to the supply [5]. To address these issues, we present a background calibrated supply tracking clock modulator (STCM) that optimally adjusts the clock frequency to the supply by placing it at the end of the clock buffer, instead of before.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1076 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116025243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration","authors":"Yu-Sian Liao, Wei-Zen Chen","doi":"10.1109/A-SSCC53895.2021.9634816","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634816","url":null,"abstract":"As the data rates of high speed SERDES continue to evolve from tens to hundreds of Gbps, higher order modulation schemes such as pulse amplitude modulation (PAM) or quadrature amplitude modulation (QAM) are widely adopted in wireline communications to boost up the spectral efficiency. Additionally, digital signal processing (DSP) based transceivers become the main stream to cope with the channel non-idealities, such as frequency dependent channel loss, cross talk, and signal reflections. High speed ADCs running at tens of GS/s are demanding at the receiver front-end and play a key role in those applications. Among them, time interleaved successive approximation register (TI-SAR) ADCs are commonly employed thanks to its digitally intensive implementation and performance improvement along with technology scaling. Limited by the sampling rate of each sub-ADC, a large number of TI-ADC banks would complicate the clock tree distribution and timing skew calibration efforts, which would lead to a higher power consumption. [1] demonstrates a flash-assisted (FA) TI-SAR structure can be utilized to enhance the conversion speed with excellent power efficiency. In this paper, a single-channel 1.75 GS/s 6-bit SAR ADC is proposed. It is designed to support 112 Gbps (56 GBaud) PAM-4 receiver through 32X TI implementation. In the DSP based receiver, the ADC output feeds into the FFE for channel equalization. Meanwhile, the ADC output is applied to clock and data recovery (CDR) circuit to generate the global sampling clock. A long latency in the TI-SAR would degrade the CDR jitter tracking capability. To circumvent the design challenges, conventional SERDES receiver AFE requires dual feedback paths. The main loop of CDR is implemented with a short latency, while the ADC loop performs as an auxiliary path for sampling phase adjustment. As the phase detector for a PAM-4 CDR inherently consists of a 2-bit quantizer, to avoid hardware redundancy and reduce system power consumption, this paper proposes a high-speed FA-SAR ADC. In this implementation, the 2 MSBs are generated by flash operation, which can be combined with the PD in CDR to accelerate phase and frequency locking. Meanwhile, it assists the succeeding SAR operation for the remaining bits conversion to avoid noise boosting in the digital FFE.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126578299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS","authors":"Xi Meng, Junqi Guo, Haoran Li, J. Yin, Pui-in Mak, R. Martins","doi":"10.1109/A-SSCC53895.2021.9634740","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634740","url":null,"abstract":"The emerging wireless systems can profit from a low-phase-noise high-frequency-band local oscillator (LO) to enable the use of dense modulation schemes over a wide signal bandwidth. When the LO frequency escalates from RF to millimeter waves, the capacitive devices (e.g., varactor and switched capacitor) tend to dominate the tank quality factor (O) of the voltage-controlled oscillator (VCO), imposing a severe trade-off between the phase noise (PN) and the frequency tuning range. Meanwhile, the technology downscaling further exacerbates this trade-off since the advanced process nodes demand more metal layers to connect transistors in a higher density, diminishing the metal thickness and thus reducing the Q of the metal-oxide-metal (MOM) capacitor. Besides, the deteriorating 1/f noise of MOS transistors in the advanced processes is another challenge faced by the VCO PN performance. Consequently, the PNs and the figure-of-merits (FoMs) of recent VCOs in 28nm CMOS [1–3] are inferior to their 65nm [4] and 40nm [5] counterparts.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126927083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A-SSCC 2021 Author Index","authors":"","doi":"10.1109/a-sscc53895.2021.9634825","DOIUrl":"https://doi.org/10.1109/a-sscc53895.2021.9634825","url":null,"abstract":"","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125460163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique","authors":"Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, G. Ahn","doi":"10.1109/A-SSCC53895.2021.9634767","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634767","url":null,"abstract":"Switched-capacitor (SC) circuits have been widely used for sampling operation of mixed-signal integrated circuits, especially in CMOS technologies. Using with amplifiers, SC circuits enable the robust implementation of the sampling network with various transfer functions. However, the kT/C noise resulting from the transistors used for switches limits the achievable signal-to-noise ratio (SNR). Therefore, achieving wide dynamic range (DR) requires a large amount of on-chip sampling capacitance. In [1], a continuous-time input stage is employed to achieve the kT/C noise free operation, which leads to considerable power and area reduction. However, the capacitive coupling used at the input will block DC signals and limit the range of suitable applications.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126257020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter","authors":"Chih-Cheng Chen, C. Hsieh","doi":"10.1109/A-SSCC53895.2021.9634791","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634791","url":null,"abstract":"Noise Shaping SAR (NS-SAR) ADC is an emerging architecture which can achieve power efficiency and high resolution simultaneously by combining the advantages of SAR operation and delta-sigma modulation. The prior residue process can be classified into two types: passive and active. For passive residue process, switching capacitor (SC) finite-impulse-response (FIR) filter [1] [2] is implemented with low power consumption. However, the passive approach suffers from the gain loss of charge sharing operation and the resulting NTF is mild. For active residue process, an active gain stage is implemented to compensate the gain loss and improve the NTF with a better noise suppression. However, the required amplifier for active approach is usually power consuming. Using open-loop dynamic amplifier [3] [4] is a compromised active solution for gain loss and power consumption, but, its gain is PVT sensitive and needs calibration with increasing design complexity. Closed-loop dynamic amplifier is reported to achieve a high PVT robustness [5], however, the multi-stage high-gain floating-inverter-based amplifier is needed to minimize the finite gain error with considerable settling time and power consumption requirement.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131272086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2.7W AC-coupled hybrid supply modulator achieving 200MHz envelope-tracking bandwidth for 5G new radio power amplifier","authors":"Peng Xu, Xueli Zhang, Peng Cao, Tingting Wei, Zhiguo Tong, Jiawei Xu, Zhiliang Hong","doi":"10.1109/A-SSCC53895.2021.9634804","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634804","url":null,"abstract":"Modern wireless communication system especially the 5G needs much higher throughput, which requires wide channel bandwidth and high peak-to-average power ratio (PAPR) envelope. This kind of signal seriously deteriorates the efficiency of power amplifier (PA). Envelope tracking (ET) is an effective way to maximize the efficiency of PA which should be operated in the power back-off region for linearity. It has been commercialized since 4G LTE era and is also being employed in 5G NR handsets [1]. The prior art envelope tracking supply modulators (ETSM) rely on the hybrid architecture, i.e. a wideband linear amplifier (LA) and a low-loss switching power modulator (SPM), to improve power efficiency. The AC-coupled hybrid ETSM [1], 3, [4] filters the DC envelope signal, leaving only the AC component to the LA. Hence, the supply voltage of the LA can be lower than the peak envelope voltage for higher efficiency. On the other hand, the bandwidth of the ETSMs is often limited to 40MHz-130MHz [1]–[4]. An even higher bandwidth to accommodate 5G New Radio (NR) remains a bottleneck because of the large output capacitor introduced by PA. A recently reported ETSM [5] achieves 200MHz bandwidth but with a rather ideal resistive load of $5 Omega$. In this paper, the ETSM is loaded with a more realistic PA model of $4 Omega //600$ pF. By utilizing diverse circuit techniques, the proposed ETSM achieves 200MHz bandwidth with 78.5% peak efficiency.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123663655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration","authors":"Yan-an Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li","doi":"10.1109/A-SSCC53895.2021.9634744","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634744","url":null,"abstract":"Infrared focal plane arrays (IRFPAs) have been widely used in industrial, scientifical and medical imaging applications [1]–[5]. Due to the limitation of the manufacturing process, material quality and other factors, IRFPAs inevitably suffer from the current non-uniformity under the same light intensity; and the bad pixel with extreme photoelectric response which significantly degrade the quality of the image. In addition to the bad pixel compensation and non-uniformity calibration, some other processing algorithms are often implemented for IRFPAs to improve the image quality, such as spatial filtering, background subtraction, etc. Conventionally the image processing algorithms are implemented by caching one or more frames of images via on-chip memory or FPGA first, and then the algorithmic processing is performed on the cashed image data. It takes up large amounts of resource space to store the data, and the need of multiple image algorithms not only increases the system complexity but also prolongs the processing time significantly [1].","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122281440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}