2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing最新文献_第10页

Bit-Flip Aware Control-Flow Error Detection 位翻转感知控制流错误检测

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.114

G. Nazarian, Diego G. Rodrigues, Álvaro Freitas Moreira, L. Carro, G. Gaydadjiev

{"title":"Bit-Flip Aware Control-Flow Error Detection","authors":"G. Nazarian, Diego G. Rodrigues, Álvaro Freitas Moreira, L. Carro, G. Gaydadjiev","doi":"10.1109/PDP.2015.114","DOIUrl":"https://doi.org/10.1109/PDP.2015.114","url":null,"abstract":"Recent increase of transient fault rates has made processor reliability a major concern. Moreover performance improvements are required for many of today's embedded systems. At the same time software implemented fault detection remains the only option for off-the-shelf processors. Software methods, however, introduce significant performance overheads due to the additional instructions required for the detection. A good observation is that often code segments not susceptible to faults are protected. In this paper we propose a technique for systematic analysis of the bit-flip effects on the program control-flow in order to identify only those locations susceptible to control-flow errors and hence minimize the number of fault detection assertions. We instrument the code with minimal overhead, while maintaining high fault coverage level. Our experiments show that using the result of our bit-flip analysis and limiting the code instrumentation to only the susceptible locations releases 28.9% (on average) of the memory while the level of fault coverage remains the same as with full instrumentation.","PeriodicalId":285111,"journal":{"name":"2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114074592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design of Integrated Vulnerabilities Database for Computer Networks Security Analysis 面向计算机网络安全分析的综合漏洞数据库设计

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.38

A. Fedorchenko, Igor Kotenko, A. Chechulin

引用次数: 4

Optimizing OLAP Cubes Construction by Improving Data Placement on Multi-nodes Clusters 通过改进多节点集群上的数据放置来优化OLAP多维数据集构造

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.45

Billel Arres, N. Kabachi, Omar Boussaïd

引用次数: 6

Impact of Data Sharing on Co-Running Embedded Applications in Multi-core System 数据共享对多核系统协同运行嵌入式应用的影响

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.88

A. Korotaeva, W. Nebel

引用次数: 0

System-Level State Equality Detection for the Formal Dynamic Verification of Legacy Distributed Applications 遗留分布式应用形式化动态验证的系统级状态相等检测

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.95

Marion Guthmuller, M. Quinson, G. Corona

引用次数: 5

Heterogeneous Acceleration of Volumetric JPEG 2000 体积JPEG 2000的异构加速

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.112

Jan G. Cornelis, J. Lemeire, T. Bruylants, P. Schelkens

引用次数: 1

The Tag Filter Cache: An Energy-Efficient Approach 标签过滤器缓存:一种节能方法

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.58

Joan J. Valls, J. Sahuquillo, Alberto Ros, M. E. Gómez

{"title":"The Tag Filter Cache: An Energy-Efficient Approach","authors":"Joan J. Valls, J. Sahuquillo, Alberto Ros, M. E. Gómez","doi":"10.1109/PDP.2015.58","DOIUrl":"https://doi.org/10.1109/PDP.2015.58","url":null,"abstract":"Power consumption in current high-performance chip multiprocessors (CMPs) has become a major design concern. The current trend of increasing the core count aggravates this problem. On-chip caches consume a significant fraction of the total power budget. Most of the proposed techniques to reduce the energy consumption of these memory structures are at the cost of performance, which may become unacceptable for high-performance CMPs. On-chip caches in multi-core systems are usually deployed with a high associativity degree in order to enhance performance. Even first-level caches are currently implemented with eight ways. The concurrent access to all the ways in the cache set is costly in terms of energy. In this paper we propose an energy-efficient cache design, namely the Tag Filter Cache (TF-Cache) architecture, that filters some of the set ways during cache accesses, allowing to access only a subset of them without hurting the performance. Our cache for each way stores the lowest order tag bits in an auxiliary bit array and these bits are used to filter the ways that do not match those bits in the searched block tag. Experimental results show that, on average, the TF-Cache architecture reduces the dynamic power consumption up to 74.9% and 85.9% when applied to the L1 and L2 cache, respectively, for the studied applications.","PeriodicalId":285111,"journal":{"name":"2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123936202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Dynamic Guaranteed Service Communication on Best-Effort Networks-on-Chip 片上网络的动态保证服务通信

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.47

Peter Munk, Matthias Freier, Jan Richling, Jian-Jia Chen

{"title":"Dynamic Guaranteed Service Communication on Best-Effort Networks-on-Chip","authors":"Peter Munk, Matthias Freier, Jan Richling, Jian-Jia Chen","doi":"10.1109/PDP.2015.47","DOIUrl":"https://doi.org/10.1109/PDP.2015.47","url":null,"abstract":"In order to execute applications under real-time constraints on many-core processors with a Network-on-Chip (NoC), guaranteed service (GS) communication with guaranteed end-to-end latency and bandwidth is required. Several hardware-based solutions for GS communication have been proposed in literature. However, commercially available many-core processors, e.g., Tilera's Tile Pro64 or Adapt Eva's Epiphany, do not support such features. In this paper, we propose a software solution that allows GS communication on 2D-mesh packet-switching NoCs. Our investigation is based on a hardware model that is applicable to commercially available processors, which include multiple NoCs to separate request and response packets and support only best-effort communication. We prove that a common upper bound of the injection rate for all sources limits the congestion which leads to an upper bound of the worst-case transmission latency (WCTL) for any transmission, i.e., the combination of a request and a response packet. Furthermore, our approach supports arbitrary transmission streams that can be modified at runtime without violating the upper bound of the WCTL, as long as the injection rate is not violated. This enables adaptive features such as task migration or dynamic scheduling policies. Experiments evaluate our solution for different traffic patterns.","PeriodicalId":285111,"journal":{"name":"2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123945489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Mutual Influence of Application- and Platform-Level Adaptations on Energy-Efficient Computing 应用级和平台级适应对节能计算的相互影响

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.9

K. Rybina, W. Dargie, René Schöne, S. Malakuti

引用次数: 4

An Efficient Implementation of Ant Colony Optimization on GPU for the Satisfiability Problem 求解可满足性问题的高效GPU蚁群算法

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Pub Date : 2015-03-04 DOI: 10.1109/PDP.2015.59

Hassan A. Youness, Aziza Ibraheim, M. Moness, M. Osama

引用次数: 10