Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors最新文献_第3页

Adaptive routing in Clos networks Clos网络中的自适应路由

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528820

P. Franaszek, C. J. Georgiou, Chung-Sheng Li

引用次数: 3

Precise exception handling for a self-timed processor 自定时处理器的精确异常处理

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528787

W. Richardson, E. Brunvand

引用次数: 8

A novel architecture for an ATM switch 一种新颖的ATM交换机架构

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528831

Jin Li, Chuan-lin Wu

引用次数: 4

Memory organization for video algorithms on programmable signal processors 可编程信号处理器上视频算法的存储器组织

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528922

E. D. Greef, F. Catthoor, H. Man

{"title":"Memory organization for video algorithms on programmable signal processors","authors":"E. D. Greef, F. Catthoor, H. Man","doi":"10.1109/ICCD.1995.528922","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528922","url":null,"abstract":"In this paper, several DSP system design principles are presented which are valid for a large class of memory-intensive algorithms. Our main focus lies on the optimization of the memory and I/O, since these are dominant cost factors in the domain of video and imaging applications. This has resulted in several formalizable mapping principles, which allow to prevent the memory from becoming a bottleneck. First, it as shown that for this class of applications, compile-time data caching decisions not only have a large effect on the performance, but also can have an even larger effect on the overall system cost and power consumption. This is illustrated by means of experiments in which the whole range of no cache up to large cache sizes is scanned. Next, it is shown that when enforcing constant I/O rates to reduce buffer sizes, the area gain may be far more important than the small performance decrease associated with it. A technique to achieve this in an efficient way is proposed. The main test-vehicle which is used throughout the paper to demonstrate our approach is the class of motion estimation type algorithms.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Performance assessment of embedded Hw/Sw systems 嵌入式软硬件系统的性能评估

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528790

J. P. Calvez, O. Pasquier

{"title":"Performance assessment of embedded Hw/Sw systems","authors":"J. P. Calvez, O. Pasquier","doi":"10.1109/ICCD.1995.528790","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528790","url":null,"abstract":"Performance assessment of embedded Hw/Sw systems built with various types of VLSI components, i.e. heterogeneous multi-processor architectures, is important to help the development of complex real-time applications. To design such a tool, two issues are to be solved, relevant information gathered simultaneously on several components without disturbing the application behavior, and the display of the performance results in a way which is easily interpreted by designers. This paper presents an interesting solution for the two above issues. We first describe what the goal for designers is and what kind of applications are concerned. Then we describe the principle of collecting an event trace and the technique to evaluate the selected performance indexes. The monitoring technique, based on a specific ASIC, is nonintrusive and allows to capture real-time event occurrences from software tasks and even from hardware functions implemented in ASICs. Each event is automatically time-stamped, collected and processed in real-time to evaluate the performance indexes selected by the designer. We also describe the display tool which clearly shows to the designer the results according to different representations. This technique and the associated real-time performance analyzer are integrated in a whole development process based on the MCSE methodology.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130375269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Test generation for multiple state-table faults in finite-state machines 有限状态机中多状态表故障的测试生成

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528824

I. Pomeranz, S. Reddy

引用次数: 33

Testing-what's missing? An incomplete list of challenges 测试的失踪吗?一份不完整的挑战清单

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528843

S. Reddy

{"title":"Testing-what's missing? An incomplete list of challenges","authors":"S. Reddy","doi":"10.1109/ICCD.1995.528843","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528843","url":null,"abstract":"Summary form only given. As the testing area becomes mature, the challenges it poses shift. We describe some of these challenges and how they are addressed in recent works in various areas of testing. In recent years, the formulations of testing problems have changed from \"given a problem, find a solution\" to \"given a problem and quality measures, find a high-quality solution\". Quality guarantees in the form of lower and upper bounds and optimal solutions are derived, in addition to the more conventional demonstration of performance on benchmark circuits. Quality guarantees allow one to measure the distance between a given solution and an optimal solution, and provide criteria for evaluating a new procedure that are more effective than comparison to previously proposed procedures. We review several areas where bounds and optimal solutions have been found. Most procedures are specific to a given problem, and cannot be reused to solve other problems. In contrast, general-purpose paradigms allow a large variety of problems to be solved cost-effectively by plugging in the appropriate procedures into the same algorithm. Such paradigms allow faster program development and reuse of expertise acquired in solving other problems under the same paradigm. We describe several attempts at using existing paradigms and developing new ones, that successfully compete with special-purpose procedures. Recent works address testing issues at increasingly higher levels of the design cycle and offer an integrated treatment of design and test. High-level failure models are considered as well as solutions that are completely independent of a failure model. We describe some of these works and the advantages of the two directions. We conclude with an (incomplete) list of challenges for future research.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"52 27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124619820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-dimensional interleaving for time-and-memory design optimization 多维交错时间和记忆设计优化

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528905

N. Passos, E. Sha, L. Chao

引用次数: 16

Distributed automatic test pattern generation with a parallel FAN algorithm 基于并行FAN算法的分布式自动测试模式生成

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528944

Stefan Radtke, J. Bargfrede, W. Anheier

引用次数: 1

The resource conflict methodology for early-stage design space exploration of superscalar RISC processors 超大规模RISC处理器早期设计空间探索的资源冲突方法

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528798

J. Wellman, E. Davidson

引用次数: 9