Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors最新文献

An empirical study of datapath, memory hierarchy, and network in SIMD array architectures SIMD阵列架构中数据路径、内存层级和网络的实证研究

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528921

M. Herbordt, C. Weems

引用次数: 4

Performance estimation for real-time distributed embedded systems 实时分布式嵌入式系统的性能评估

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528792

Ti-Yen Yen, W. Wolf

引用次数: 139

Write buffer design for cache-coherent shared-memory multiprocessors 缓存一致共享内存多处理器的写缓冲区设计

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528915

F. Mounes-Toussi, D. Lilja

引用次数: 9

Minimal self-correcting shift counters 最小的自校正移位计数器

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528925

A.M. Tokarnia, A. Peterson

引用次数: 0

Logic synthesis for a single large look-up table 单个大型查询表的逻辑综合

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528842

R. Murgai, M. Fujita, F. Hirose

{"title":"Logic synthesis for a single large look-up table","authors":"R. Murgai, M. Fujita, F. Hirose","doi":"10.1109/ICCD.1995.528842","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528842","url":null,"abstract":"Logic synthesis for look-up tables (LUTs) has received much attention in the past few years, since Xilinx introduced its LUT-based field-programmable gate array (FPGA) architectures. An m-input LUT can implement any Boolean function of up to m inputs. So the goal of synthesis for such architectures has been to synthesize a circuit in which each function can be implemented by one m-LUT such that either the total number of functions or the number of levels of the circuit is minimized. In this work, we focus on a different though related problem: synthesize the given circuit on a single memory or LUT L, which has a capacity of M bits. In addition to satisfying the memory constraint M, we also wish to minimize the total number of functions to be implemented. The main motivation for the problem comes from the problem of minimizing the simulation time on a hardware accelerator for logic simulation. This accelerator uses memory as a logic primitive. In fact, the problem is also relevant in the context of compile-code or software simulation. Another situation where the problem arises is in synthesis for the FPGA architectures being proposed that have on-chip memory for storing programs and data. The unused memory locations can be used to store logic functions. We show that the existing LUT synthesis methods are inadequate to solve this problem. We propose techniques to solve the problem and present experimental evidence to demonstrate their effectiveness.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128516578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Interrupt-based hardware support for profiling memory system performance 基于中断的硬件支持，用于分析内存系统性能

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528917

A. Goldberg, J. Trotter

引用次数: 4

DART: delay and routability driven technology mapping for LUT based FPGAs 基于LUT的fpga的延迟和可路由性驱动技术映射

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528841

A. Lu, E. Dagless, J. Saul

引用次数: 13

Multiprocessor design verification for the PowerPC 620 microprocessor powerpc620微处理器的多处理器设计验证

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528809

C. Montemayor, M. Sullivan, Jen-Tien Yen, P. Wilson, R. Evers

引用次数: 10

The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor PowerPC 603e微处理器:一种增强型、低功耗、超标量微处理器

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528810

C. Montemayor, M. Sullivan, Jen-Tien Yen, P. Wilson, R. Evers, K. R. Kishore

{"title":"The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor","authors":"C. Montemayor, M. Sullivan, Jen-Tien Yen, P. Wilson, R. Evers, K. R. Kishore","doi":"10.1109/ICCD.1995.528810","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528810","url":null,"abstract":"The PowerPC 603e microprocessor is a high performance, low cost, low power microprocessor designed for use in portable computers. The 603e is an enhanced version of the PowerPC 603 microprocessor and extends the performance range of the PowerPC microprocessor family of portable products. The enhancements include increasing the frequency to 100 MHZ doubling the on-chip instruction and data caches to 16 Kbytes each, increasing the cache associativity to 4-way set-associative, adding an extra integer unit, and increasing the throughput of stores and misaligned accesses. Three new bus modes are added to allow for more flexibility in system design. The estimated performance of the 603e at 100 MHz is 120 SPECint92 and 105 SPECfp92. The 603e is fabricated in the same 3.3 volt, 0.5 micron, four-level metal technology as the 603 and contains 2.6 million transistors. The die size is 98 mm/sup 2/. The typical power consumption of the 603e at 100 MHz is 3 watts. Like the 603, the 603e provides three software controllable power-down modes to further extend power saving capability.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125252690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

SSM-MP: more scalability in shared-memory multi-processor SSM-MP:在共享内存多处理器中具有更高的可伸缩性

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI: 10.1109/ICCD.1995.528923

Shigeaki Iwasa, Shu Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, H. Sakai, M. Saito

引用次数: 1