Shigeaki Iwasa, Shu Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, H. Sakai, M. Saito
{"title":"SSM-MP:在共享内存多处理器中具有更高的可伸缩性","authors":"Shigeaki Iwasa, Shu Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, H. Sakai, M. Saito","doi":"10.1109/ICCD.1995.528923","DOIUrl":null,"url":null,"abstract":"Bus-based shared-memory multi-processors (SM-MP) have successfully been used commercially, since implementation requires no drastic changes to the programming paradigm. In this paper we propose the memory structure called SSM-MP (Scalable shared-memory multi-processors), aimed to shorten the cache refill latency and to relax the bus bottle neck problem. In this machine, main memory consists of local memories dedicated to each of the processors and something called MTag. MTag is a small piece of hardware that filters out bus traffic headed to the system bus and maintains cache coherency. A popular UNIX (SVR4 ES/MP) was ported. Original OS code works well due to its natural locality. Furthermore, by allocating tasks to the local memory, we were able to reduce the system bus traffic to nearly a quarter. SSM-MP is an effective approach in building a multi-processor system with a medium number (4-32) of processors.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"SSM-MP: more scalability in shared-memory multi-processor\",\"authors\":\"Shigeaki Iwasa, Shu Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, H. Sakai, M. Saito\",\"doi\":\"10.1109/ICCD.1995.528923\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Bus-based shared-memory multi-processors (SM-MP) have successfully been used commercially, since implementation requires no drastic changes to the programming paradigm. In this paper we propose the memory structure called SSM-MP (Scalable shared-memory multi-processors), aimed to shorten the cache refill latency and to relax the bus bottle neck problem. In this machine, main memory consists of local memories dedicated to each of the processors and something called MTag. MTag is a small piece of hardware that filters out bus traffic headed to the system bus and maintains cache coherency. A popular UNIX (SVR4 ES/MP) was ported. Original OS code works well due to its natural locality. Furthermore, by allocating tasks to the local memory, we were able to reduce the system bus traffic to nearly a quarter. SSM-MP is an effective approach in building a multi-processor system with a medium number (4-32) of processors.\",\"PeriodicalId\":281907,\"journal\":{\"name\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1995.528923\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1995.528923","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SSM-MP: more scalability in shared-memory multi-processor
Bus-based shared-memory multi-processors (SM-MP) have successfully been used commercially, since implementation requires no drastic changes to the programming paradigm. In this paper we propose the memory structure called SSM-MP (Scalable shared-memory multi-processors), aimed to shorten the cache refill latency and to relax the bus bottle neck problem. In this machine, main memory consists of local memories dedicated to each of the processors and something called MTag. MTag is a small piece of hardware that filters out bus traffic headed to the system bus and maintains cache coherency. A popular UNIX (SVR4 ES/MP) was ported. Original OS code works well due to its natural locality. Furthermore, by allocating tasks to the local memory, we were able to reduce the system bus traffic to nearly a quarter. SSM-MP is an effective approach in building a multi-processor system with a medium number (4-32) of processors.