2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)最新文献_第2页

LearnLoc: A framework for smart indoor localization with embedded mobile devices LearnLoc:基于嵌入式移动设备的智能室内定位框架

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.5555/2830840.2830845

S. Pasricha, Viney Ugave, Charles W. Anderson, Qi Han

引用次数: 34

seBoost: Selective boosting for heterogeneous manycores seBoost:对异构多核的选择性增强

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331373

Santiago Pagani, M. Shafique, Heba Khdr, Jian-Jia Chen, J. Henkel

引用次数: 18

R2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores R2Cache:用于多核的可靠性感知可重构的最后一级缓存架构

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331362

F. Kriebel, Arun K. Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, M. Shafique, J. Henkel

{"title":"R2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores","authors":"F. Kriebel, Arun K. Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, M. Shafique, J. Henkel","doi":"10.1109/CODESISSS.2015.7331362","DOIUrl":"https://doi.org/10.1109/CODESISSS.2015.7331362","url":null,"abstract":"On-chip last-level caches in multicore systems are one of the most vulnerable components to soft errors. However, vulnerability to soft errors highly depends upon the parameters and configuration of the last-level cache, especially when executing different applications. Therefore, in a reconfigurable cache architecture, the cache parameters can be adapted at run-time to improve its reliability against soft errors. In this paper we propose a novel reliability-aware reconfigurable last-level cache architecture (R2Cache) for multicore systems. It provides reliability-wise efficient cache configurations (i.e. cache parameter selection and cache partitioning) for different concurrently executing applications under user-provided tolerable performance overheads. To enable run-time adaptations, we also introduce a lightweight online vulnerability predictor that exploits the knowledge of performance metrics like number of L2 misses to accurately estimate the cache vulnerability to soft errors. Based on the predicted vulnerabilities of different concurrently executing applications in the current execution epoch, our run-time reliability manager reconfigures the cache such that, for the next execution epoch, the total vulnerability for all concurrently executing applications is minimized. In scenarios where single-bit error correction for cache lines may be afforded, vulnerability-aware reconfigurations can be leveraged to increase the reliability of the last-level cache against multi-bit errors. Compared to state-of-the-art, the proposed architecture provides 24% vulnerability savings when averaged across numerous experiments, while reducing the vulnerability by more than 60% for selected applications and application phases.","PeriodicalId":281383,"journal":{"name":"2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127837024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Fast parallel application and multiprocessor design space exploration from sequential code 从顺序代码探索快速并行应用和多处理器设计空间

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331379

V. Schwambach, Sébastien Cleyet-Merle, Alain Issard, S. Mancini

引用次数: 0

An online wear state monitoring methodology for off-the-shelf embedded processors 一种现成嵌入式处理器的在线磨损状态监测方法

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331374

Srinath Arunachalam, Thidapat Chantem, R. Dick, X. Hu

{"title":"An online wear state monitoring methodology for off-the-shelf embedded processors","authors":"Srinath Arunachalam, Thidapat Chantem, R. Dick, X. Hu","doi":"10.1109/CODESISSS.2015.7331374","DOIUrl":"https://doi.org/10.1109/CODESISSS.2015.7331374","url":null,"abstract":"The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [13, 5] that strongly depends on temperature. NBTI manifests in the form of increased circuit delays which can lead to timing failures and processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this paper, we propose a lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither data on the threshold voltage and critical paths nor additional hardware. Our methodology can also be extended to predict the wear progression due to some other dominant IC failure mechanisms. Experiments on embedded processors provide insights on NBTI wear progression over time. This knowledge can be used to design real-time embedded systems that explicitly consider runtime wear progression to increase predictability and maintain lifetime reliability requirements.","PeriodicalId":281383,"journal":{"name":"2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130249674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

An approximate compressor for wearable biomedical healthcare monitoring systems 用于可穿戴生物医学保健监测系统的近似压缩器

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.5555/2830840.2830855

Farzad Samie, L. Bauer, J. Henkel

{"title":"An approximate compressor for wearable biomedical healthcare monitoring systems","authors":"Farzad Samie, L. Bauer, J. Henkel","doi":"10.5555/2830840.2830855","DOIUrl":"https://doi.org/10.5555/2830840.2830855","url":null,"abstract":"Technology advancements as well as the Internet-of-Things paradigm enable the design of wearable personal healthcare monitoring systems. Ultra-low-power design is a challenging area for these battery-operated wearable devices, where the energy supply is limited and hardware resources are scarce. Some biomedical applications tolerate small errors in the values of the biosignal or small degradation in the quality, which can be exploited to reduce the energy requirements. This paper presents an approximate compression technique for biosignals in a wearable healthcare monitoring system. It takes advantage of error tolerance in biosignals and finds the shortest code to compress the data while keeping the error in an acceptable range. Our approximate compressor does not demand any hardware modification and thus can be used in existing wearable devices. The proposed approach for reducing the size of the Huffman table can save 1 MBit storage, on average. It also makes our approximate compressor suitable for runtime adaptation, i.e. creating a new Huffman table based on updated values. Compared to state-of-the-art, our experimental results show up to 60% reduction in data size that is to be transmitted via radio. As wireless communication contributes significantly to the total energy consumption of wearable devices, this improvement can increase the battery lifetime of our healthcare monitoring prototype from 7 days to 10 days.","PeriodicalId":281383,"journal":{"name":"2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127909297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Hardware synthesis from a recursive functional language 硬件合成从递归函数语言

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331371

Kuangya Zhai, Richard Townsend, L. Lairmore, Martha A. Kim, S. Edwards

引用次数: 18

The shift to multicores in real-time and safety-critical systems 在实时和安全关键型系统中向多核的转变

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331385

Selma Saidi, R. Ernst, S. Uhrig, Henrik Theiling, B. Dinechin

{"title":"The shift to multicores in real-time and safety-critical systems","authors":"Selma Saidi, R. Ernst, S. Uhrig, Henrik Theiling, B. Dinechin","doi":"10.1109/CODESISSS.2015.7331385","DOIUrl":"https://doi.org/10.1109/CODESISSS.2015.7331385","url":null,"abstract":"In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multi-core/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.","PeriodicalId":281383,"journal":{"name":"2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125917887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 71

Computer security by hardware-intrinsic authentication 硬件内在认证的计算机安全

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331377

Caio Hoffman, M. Côrtes, Diego F. Aranha, G. Araújo

{"title":"Computer security by hardware-intrinsic authentication","authors":"Caio Hoffman, M. Côrtes, Diego F. Aranha, G. Araújo","doi":"10.1109/CODESISSS.2015.7331377","DOIUrl":"https://doi.org/10.1109/CODESISSS.2015.7331377","url":null,"abstract":"The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things (IoT), has raised a number of challenges for the design of Systems-on-Chip (SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.","PeriodicalId":281383,"journal":{"name":"2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130061887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Energy efficient FFT implementation through stage skipping and merging 通过阶段跳过和合并实现节能FFT

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2015-10-04 DOI: 10.1109/CODESISSS.2015.7331378

Namita Sharma, P. Panda, F. Catthoor

引用次数: 0