Hardware synthesis from a recursive functional language

Kuangya Zhai, Richard Townsend, L. Lairmore, Martha A. Kim, S. Edwards
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引用次数: 18

Abstract

Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to SystemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.
硬件合成从递归函数语言
几十年前,硬件描述语言中的抽象在寄存器传输级别停滞不前,但很少有替代方法取得了很大的成功,部分原因是它们在表达性方面只提供了有限的增益。我们建议做一个更大的跳跃:一个从行为功能规范合成硬件的编译器。在应用一系列保持语义的转换之前,我们的编译器将一般的Haskell程序转换为受限制的中间表示,最后以简单的语法导向转换为SystemVerilog。在这里,我们给出了这个编译器的总体框架,重点是所涉及的中间表示和我们将一般递归函数转换为等效硬件的方法。最后,我们用实验结果来描述编译器生成的电路的性能和资源使用情况。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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