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2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)最新文献

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Failure Analysis of Multi-layer Ceramic Capacitors under Board Level Shock Environment 多层陶瓷电容器在板级冲击环境下的失效分析
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487147
Jialu Li, Jiahao Zhao, Zheng You
{"title":"Failure Analysis of Multi-layer Ceramic Capacitors under Board Level Shock Environment","authors":"Jialu Li, Jiahao Zhao, Zheng You","doi":"10.1109/EDSSC.2018.8487147","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487147","url":null,"abstract":"The possible failure modes of the multi-layer ceramic capacitor (MLCC) under board-level shock environment are studied through modeling, simulation and experiment. In this work, a finite element model is established to simulate the stress distribution. A Machete hammer test system is set up to measure the shock resistance of MLCC. It is indicated that pad peeling off, fracture of metal electrodes and degradation of electrical parameters are the main failure phenomena of MLCC under board-level impact.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121447110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design Technology of High Linearity DAC for Large Array CMOS Image Sensor 大阵列CMOS图像传感器高线性DAC设计技术
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487151
Zhongjie Guo, N. Yu
{"title":"Design Technology of High Linearity DAC for Large Array CMOS Image Sensor","authors":"Zhongjie Guo, N. Yu","doi":"10.1109/EDSSC.2018.8487151","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487151","url":null,"abstract":"This paper presents a high precision DAC with seamless switch technique for large array CMOS image sensor to calibrate column fixed pattern noise and black level. Through the deep analysis on non-ideal factor and error source of piecewise DAC in multichannel, the high precision seamless switch technique has been researched. The adaptive signal chain switch technique according to the high to low subsection is developed in this paper, so the seamless switch is realized, and the convert accuracy is boosted. A prototype high intrinsic DR and low column FPN CMOS image sensor chip consisting of 64M 4T active pixel sensor (APS) array was designed and fabricated in 55nm CMOS 1P4M standard process, 75dB intrinsic DR and 0.06% column-to-column fixed pattern noise are achieved.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126055526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis on Transfer Efficiency of Five Different Antenna Configurations in Short-Distance Wireless Power Transfer 近距离无线电力传输中5种不同天线配置的传输效率分析
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487103
Wentao Xiong, Mei Jiang, Guanlong Huang, Haoxin Chen
{"title":"Analysis on Transfer Efficiency of Five Different Antenna Configurations in Short-Distance Wireless Power Transfer","authors":"Wentao Xiong, Mei Jiang, Guanlong Huang, Haoxin Chen","doi":"10.1109/EDSSC.2018.8487103","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487103","url":null,"abstract":"This paper proposes four newly-designed antenna configurations for the applications of short-distance wireless power transfer. The antennas are developed from a traditional circular loop antenna, which have a structural feature in common that all of them are in enclosed shape. Four proposed designs aim to improve the transfer efficiency. In this work, the transmitting antenna faces to the receiving antenna with a distance of 12 cm in the wireless power transfer system. Results show that two of them have better performance of transferring power than the other two and the conventional design.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128423106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Novel Cryo-controlled Nucleation Technique for High-efficiency Perovskite Solar Cells 高效钙钛矿太阳能电池的低温控核新技术
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487152
A. Ng, Z. Ren, S. Cheung, A. Djurišić, S. Su, Gang Li, C. Surya
{"title":"Novel Cryo-controlled Nucleation Technique for High-efficiency Perovskite Solar Cells","authors":"A. Ng, Z. Ren, S. Cheung, A. Djurišić, S. Su, Gang Li, C. Surya","doi":"10.1109/EDSSC.2018.8487152","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487152","url":null,"abstract":"A novel cryo-controlled nucleation technique is developed to grow mixed halide perovskite for solar cells (PSCs). The abrupt decrease in the ambient temperature results in a supersaturation condition in the precursor film prepared by the spin coating process, leading to form uniform nucleation sites for subsequent crystal growth. The low temperature ambient retards the pre-mature crystallization of the perovskite film in the early stage before a uniform seed layer is obtained. This film deposition approach ensures excellent uniformity of the nucleation layers and, subsequently, higher quality perovskite films. A power conversion efficiency (PCE) of 21.4 % for the champion PSC can be achieved by the proposed perovskite growth technique.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"88 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126314777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Performance Graphene/Silicon Photodetectors and Image Sensors 高性能石墨烯/硅光电探测器和图像传感器
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487134
Yang Xu
{"title":"High Performance Graphene/Silicon Photodetectors and Image Sensors","authors":"Yang Xu","doi":"10.1109/EDSSC.2018.8487134","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487134","url":null,"abstract":"To solve the typical problems of silicon-based invisible photodetectors and image sensors, we focus on the ultraviolet (UV), infrared (IR) photodetection and their imaging integration system. In recent years, we have achieved the following systematic research outcomes: 1) By proposing a new silicon-graphene synergistic absorption theory and using the silicon-on-insulator (SOI) integrated with graphene structure, we broke the limit of traditional silicon-based UV detection, and fabricated high-speed UV photodetectors and imagers; 2) By proposing a cascade structure combined with plasmon resonant absorption, we fabricated high-performance Silicon-based IR photodetectors and imagers; 3) By integrating large photodetector arrays with signal processing circuits, we established high-performance silicon-based broadband imaging system for potential applications.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126351636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Carbon Nanotube Lateral Field Emission Device with Embedded Field Effect Transistor 嵌入场效应晶体管的碳纳米管侧向场发射器件
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487091
Y. Yang, S. Huo, L. Jiang, Y. Kong, T. Chen, Hang Zhou, A. S. Teh, T. Butler, D. Hasko, G. Amaratunga
{"title":"Carbon Nanotube Lateral Field Emission Device with Embedded Field Effect Transistor","authors":"Y. Yang, S. Huo, L. Jiang, Y. Kong, T. Chen, Hang Zhou, A. S. Teh, T. Butler, D. Hasko, G. Amaratunga","doi":"10.1109/EDSSC.2018.8487091","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487091","url":null,"abstract":"A novel device structure that combines field emission and field effect transistor (FET) on a laterally grown individual semiconducting singlewalled carbon nanotube (SWNT) is proposed and realized. The SWNT serves as both the channel of the FET and the field emitter. The emission current is restricted to the supply current from the FET and hence subject to the gate modulation. The bias conditions on either device are self-adaptive to satisfy current continuity. The measurement results demonstrate good emission current stability and effective gate control over the emission characteristics. This novel type of device could establish a new approach to develop miniaturized field emission devices with superior characteristics for chip-level integration.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Flexible Artificial Synapse for Neuromorphic System 神经形态系统的柔性人工突触
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487170
Kunlong Yang, Sijian Yuan, Y. Zhan, Lirong Zheng, F. Seoane
{"title":"A Flexible Artificial Synapse for Neuromorphic System","authors":"Kunlong Yang, Sijian Yuan, Y. Zhan, Lirong Zheng, F. Seoane","doi":"10.1109/EDSSC.2018.8487170","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487170","url":null,"abstract":"Neuromorphic computing, as a new paradigm, highlighted for its highly parallel, energy efficient features, has attracted a lot of attention. The hardware implementation for a neuromorphic system proposes the strong desire for suitable building blocks. The synaptic device is a very promising solution because of its stimulation-history-related response, which fits the nature of a neural network. In this work, an artificial synapse based on a memristive transistor fabricated by a simple process is realized. The device not only shows multi-level states which is the main feature of a memristor and is essential to hardware implementation neuromorphic system, but also exhibits physical flexibility, a feature that supports wearable and portable electronics. On this basis, a proof-of-feasibility simulation using the experimental data is performed to realize the pattern classification.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124510236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Visible Light Communication System-on-a-Chip 可见光通信片上系统
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487107
Fei Lu, Z. Dong, Li Wang, Albert Z. H. Wang
{"title":"Visible Light Communication System-on-a-Chip","authors":"Fei Lu, Z. Dong, Li Wang, Albert Z. H. Wang","doi":"10.1109/EDSSC.2018.8487107","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487107","url":null,"abstract":"This paper reviews a fully integrated transceiver designed in an 180nm BCD process for light-emitting diode (LED) based visible light communication (VLC) system-on-a-chip (SoC). The VLC transceiver SoC consists of Manchester encoder/decoder, high accuracy bandgap reference, phase lock loop (PLL), multistage amplifier, trans-impedance amplifier (TIA), LED driver and ESD protection. A feed-forward equalizer is used to boost the LED bandwidth for high data rate wireless streaming. Measurement demonstrates wireless streaming of data through visible light using commercial LEDs.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Asynchronous Pipeline based Implementation of Membrane Potential of IF model 基于异步流水线的中频膜电位模型实现
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487125
Feiyang Yu, G. Feng, Juxia Xiong, Jinzhao Wu, Jinlan Wang, Anping He
{"title":"An Asynchronous Pipeline based Implementation of Membrane Potential of IF model","authors":"Feiyang Yu, G. Feng, Juxia Xiong, Jinzhao Wu, Jinlan Wang, Anping He","doi":"10.1109/EDSSC.2018.8487125","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487125","url":null,"abstract":"With the development of artificial neural network (ANN), the conflict between performance, power consumption, and volume becomes more obvious. The spiking neuron network(SNN) is the main brain-like ANN model, of which the calculation of membrane potential is the key. Since the efficiency of this type of computation is main consideration of determining the entire neural network, we introduce a design characterized by a relatively lightweight and simple structure in an asynchronous way, which is also more compatible with the SNN. We also verify our design with FPGA successful.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133291330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions 高性能硅/硅基隧道场效应管的设计:策略与解决方案
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487104
S. Chung, E. Hsieh, Y. B. Zhao, J. Lee, M. H. Lee
{"title":"The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions","authors":"S. Chung, E. Hsieh, Y. B. Zhao, J. Lee, M. H. Lee","doi":"10.1109/EDSSC.2018.8487104","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487104","url":null,"abstract":"The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. First, the concept of a face-tunneling scheme to provide a sufficient improvement over the conventional point tunneling has been justified by an experiment. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, face-tunneling FET (f-TFET) can be enhanced in its $mathrm {I}_{mathrm {on}}$ current. This work shows $mathrm {I}_{mathrm {on}}$ of f-TFET with one-order magnitude $mathrm {I}_{mathrm {on}}$ enhancement than that of point-TFET(control), and the longer the gate length is, the higher the $mathrm {I}_{mathrm {on}}$ becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control. This can be better improved by careful treatment of a special design epi-channel, Next, further improvement of the TFET performance has been proposed by a further design of an improved epitaxial SiGe-based channel structure. The design is based on a raised-drain structure with further improvement on the Ion current and much lower S. S. down to 28mV/dec.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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