Min Kyung An, Nhat X. Lam, D. Huynh, Trac N. Nguyen
{"title":"Connectivity in Wireless Sensor Networks in the SINR Model","authors":"Min Kyung An, Nhat X. Lam, D. Huynh, Trac N. Nguyen","doi":"10.1109/MASCOTS.2012.26","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.26","url":null,"abstract":"In this paper, we study the Minimum Channel Assignment (MCA) problem for strong connectivity in wireless sensor networks in the physical model known as Signal-to-Interference-Noise-Ratio (SINR). The main issue is to compute a minimum channel assignment that yields a strongly-connected communication graph spanning all nodes such that the nodes assigned to the same channel can communicate without interference in the SINR model. The complexity measure is the number of channels, and our objective is to minimize it. We show the NP-hardness of the MCA problem, and propose an algorithm that compute a channel assignment for 2-dimensional grid networks. The algorithm produces an assignment with a constant number of channels for the network. We also propose two constant-factor approximation algorithms that yield channel assignments in which the number of channels is bounded by O(Δ), where Δ is the maximum node degree of a network. We also study the performance of the algorithms through simulation.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"20 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125951573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using Software-Defined Radio to Validate Wireless Models in Simulation","authors":"K. Mandke, S. Nettles","doi":"10.1109/MASCOTS.2012.47","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.47","url":null,"abstract":"Simulation is an efficient and powerful tool for studying wireless networking. The lack of physical layer (PHY) accuracy in many popular network simulators such as ns-2 and OPNET has been observed to produce misleading results. In this paper, we demonstrate a technique for validating the packet-level PHY models in network simulators against the physical layer of a software-defined radio testbed. Specifically, we evaluate the accuracy of model-based simulations against hybrid (i.e., joint packet and waveform) simulations of the real PHY implementation directly executing in a simulation environment. We demonstrate that this direct-execution approach is an effective means of evaluating the accuracy of packet-level PHY models from the perspectives of different protocol layers using a broad set of operating conditions. Moreover, this is an effective means of establishing when a packet-level PHY model can be used to generate trustworthy simulation results.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"64 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114125636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"NetSim-Steer: A Runtime Steering Framework for Network Simulators","authors":"S. Ciraci, B. Akyol","doi":"10.1109/MASCOTS.2012.64","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.64","url":null,"abstract":"This paper presents NetSim-Steer, a runtime steering framework for network simulators. With this framework, users can specify execution constraints for the network protocols and network models. In addition to this, users can implement steering rules to be executed when a constraint is violated. These rules allow users to alter the parameters of the protocols/models during the simulation so that they stay within the boundaries of the constraints.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122983867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Split Phase Multi-channel MAC Protocols - Formal Specification and Analysis","authors":"A. Fatni, G. Juanole","doi":"10.1109/MASCOTS.2012.73","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.73","url":null,"abstract":"The efficiency of multi-channel MAC protocols depends on the channel assignment mechanism which must coordinate the channel usage in a better way. Several multi-channel MAC approaches have been proposed in the literature. In this paper we propose a formal modelling and analysis of the multi-channel MAC protocols based on the Split Phase (SP) approach using Stochastic Timed Petri Nets (STPN). We analyze the fundamental properties of this approach.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122037251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of Multi-core Scalability Bottlenecks in Enterprise Java Workloads","authors":"X. Guerin, Wei Tan, Yanbin Liu, Seetharami R. Seelam, Parijat Dube","doi":"10.1109/MASCOTS.2012.43","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.43","url":null,"abstract":"The increasing number of cores integrated into modern processors is blurring the line between supercomputers and enterprise-grade servers. Therefore, the same attention to lock contention bottlenecks must be given to Java-based business workloads as it is given to massively parallel, high-performance computing applications, especially when it comes to characterizing global trends that would ease the transition of today's code base to tomorrow's parallel configurations. This paper first presents the characteristics of a typical Java-based business application software stack and examines the locking contentions that can appear at each level of that stack. Second, it presents scalability evaluation of three enterprise-grade, Java-based workloads and details the lock contention founds. Third, it summarizes the results of our findings, emphasizing the need for a streamlined methodology for lock-contention analysis of enterprise Java workloads.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114501079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rishiraj A. Bheda, Jesse G. Beu, Brian P. Railing, T. Conte
{"title":"Extrapolation Pitfalls When Evaluating Limited Endurance Memory","authors":"Rishiraj A. Bheda, Jesse G. Beu, Brian P. Railing, T. Conte","doi":"10.1109/MASCOTS.2012.38","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.38","url":null,"abstract":"Many new non-volatile memory technologies have been considered as a future scalable alternative to DRAM. Memory technologies such as MRAM, FeRAM, PCM have emerged as the most viable alternatives. But these memories have limited wear endurance. Practically realizable main memory systems employing these memory technologies are possible only if the wear across these memories is reduced as well as uniformly distributed. Limited endurance has resulted in extensive wear leveling research with the goal of uniformly distributing write traffic throughout available physical memory. Basic support for wear leveling is already present in existing systems, in the form of operating system paging. The Operating System (OS) changes virtual to physical translations over time. As a result, write traffic is naturally spread out. Proper evaluation of the need for wear leveling as well as the impact of the corresponding technique must take this phenomenon into account. Ignoring the effect of OS paging mechanism can result in highly inaccurate memory lifetime extrapolations. We demonstrate through simulation results, the effects of inaccurate extrapolations in the absence of OS modeling. Accurate memory lifetime simulation can take from many months to years. Although sampling techniques are commonly employed for speedup, our results show that naïve extrapolation techniques can lead to wildly different lifetime estimates. We show how sampling can be accurately applied by accounting for the different components in the write stream observed by main memory. Finally, we present a heuristic to quickly estimate memory lifetime for a given application.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126944552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yan Cui, Yingxin Wang, Yu Chen, Yuanchun Shi, Wei Han, Xin Liao, Fei Wang
{"title":"Reducing Scalability Collapse via Requester-Based Locking on Multicore Systems","authors":"Yan Cui, Yingxin Wang, Yu Chen, Yuanchun Shi, Wei Han, Xin Liao, Fei Wang","doi":"10.1109/MASCOTS.2012.42","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.42","url":null,"abstract":"In response to the increasing ubiquity of multicore processors, there has been widespread development of multithreaded applications that strive to realize their full potential. Unfortunately, lock contention within operating systems can limit the scalability of multicore systems so severely that an increase in the number of cores can actually lead to reduced performance (i.e. scalability collapse). Existing lock implementations have disadvantages in scalability, resource utilization and energy efficiency. In this work, we observe that the number of tasks requesting a lock has a significant correlation with the occurrence of scalability collapse. Based on this observation, we propose a novel lock implementation that allows tasks blocked on a lock to either spin or maintain a power-saving state according to the number of lock requesters. We call our lock implementation protocol a requester-based lock and implement it in the Linux kernel to replace its default spin lock. Based on the results of an analysis, we find that the best policy for a task waiting for a lock to become free is to enter the power saving state immediately after noticing that the lock cannot be acquired. Our lock-requester based lock scheme is evaluated using micro- and macro-benchmarks on AMD 32-core and Intel 40-core systems. Experimental results indicate our lock scheme removes scalability collapse completely for most applications. Furthermore, our method shows better scalability and energy efficiency than mutex locks and adaptive locks.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127738738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analyzing Parallelization and Program Performance in Heterogeneous MPSoCs","authors":"Chao Wang, Xi Li, Junneng Zhang, Gangyong Jia, Peng Chen, Xuehai Zhou","doi":"10.1109/MASCOTS.2012.61","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.61","url":null,"abstract":"In this paper we extend and analyze Amdahl's law to general heterogeneous MPSoC era, to find out how the speedup is affected by the parameters, including amount and speedup for microprocessors and accelerators, as well as the task partition characteristics. We also analyze the theoretical results about how the extended Amdahl's Law is applied to leverage load balancing of a heterogeneous MPSoC without the abstract limitation of base core equivalents (BCEs). A prototype on FPGA is constructed with Microblaze processors and JPEG hardware accelerators. The experimental results demonstrate that our extended model reinforces state-of-the-art performance evaluation methods for hybrid MPSoC architectures and also provide creditable new insights on the heterogeneous research communities, in particular for scalable FPGA based reconfigurable MPSoCs.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114832880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Barrier Counting in Mixed Wireless Sensor Networks","authors":"Shambhavi Srinivasa, C. Williamson, Zongpeng Li","doi":"10.1109/MASCOTS.2012.48","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.48","url":null,"abstract":"Barrier coverage problems in sensor networks involve detecting intruders that attempt to cross a region of interest. In this paper, we formulate the k-connect barrier count problem for Mixed Sensor Networks (MSNs). The k-connect barrier count problem is to find the maximum number of barriers in an arbitrary MSN where at most k distinct mobile sensors can be used to construct any given virtual edge used in a barrier. We present the solution for the k-connect barrier count problem for k ∈ {0, 1, 2} via Integer Linear Programming. Using simulation results, we show that as k increases, the density of sensors required to achieve barrier coverage decreases. The results quantitatively demonstrate the benefits of mobile sensors.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130073277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MERCURY: A Scalable and Similarity-Aware Scheme in Multi-level Cache Hierarchy","authors":"Yu Hua, Xue Liu, D. Feng","doi":"10.1109/MASCOTS.2012.49","DOIUrl":"https://doi.org/10.1109/MASCOTS.2012.49","url":null,"abstract":"The management of multi-level caching hierarchy is a critical and challenging task. Although there exist many hardware and OS-based schemes, they are difficult to be adopted in practice since they incur non-trivial overheads and high complexity. In order to efficiently deal with this challenge, we propose MERCURY, a cost-effective and lightweight hardware support to coordinate with OS-based cache management schemes. Its basic idea is to leverage data similarity to reduce data migration costs and deliver high performance. Moreover, in order to accurately and efficiently capture the data similarity, we propose to use low-complexity Locality-Sensitive Hashing (LSH). In our design, in addition to the problem of space inefficiency, we identify that a conventional LSH scheme also suffers from the problem of homogeneous data placement. To address these two problems, we design a novel Multi-Core-enabled LSH (MC-LSH) that accurately captures the differentiated similarity across data. The similarity-aware MERCURY hence efficiently partitions data into L1 cache, L2 cache and main memory based on their distinct localities, which help optimize cache utilization and minimize the pollution in the last level cache. Experiments through real-world benchmarks further corroborate the efficacy and efficiency of MERCURY.","PeriodicalId":278764,"journal":{"name":"2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117324838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}