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A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing 用于实时数字图像处理的扩展线性插值的低成本VLSI设计
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.85
Chung-Chi Lin, M. Sheu, H. Chiang, Z. Wu, Jia-Yi Tu, Chia-Hung Chen
{"title":"A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing","authors":"Chung-Chi Lin, M. Sheu, H. Chiang, Z. Wu, Jia-Yi Tu, Chia-Hung Chen","doi":"10.1109/ICESS.2008.85","DOIUrl":"https://doi.org/10.1109/ICESS.2008.85","url":null,"abstract":"This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Based on the approach, the low-cost hardware architecture with digital image scaling is designed under the real-time requirement. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. The presented architecture is implemented on the Virtex-II FPGA, and the VLSI architecture has been successfully designed and implemented with TSMC 0.13 mum standard cell library. The simulation results demonstrate that the high performance architecture of extended linear interpolation at 267 MHz with 26200 gates in a 452times452 mum2 chip is able to process digital image scaling for HDTV in real-time.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Chameleon-Based Optimistic Fair Exchange Protocol 基于变色龙的乐观公平交换协议
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.26
Xuan Yang, Zhaoping Yu, Bin Kang
{"title":"Chameleon-Based Optimistic Fair Exchange Protocol","authors":"Xuan Yang, Zhaoping Yu, Bin Kang","doi":"10.1109/ICESS.2008.26","DOIUrl":"https://doi.org/10.1109/ICESS.2008.26","url":null,"abstract":"A fair exchange protocol allows two parties to exchange items in a fair way so that either each party gets the other's item or neither party does. In this paper, we propose a key-exposure-free chameleon hashing scheme based on the discrete logarithm assumption, and prove that it enjoys all advantages of previous schemes: collision resistant, semantic security, message hiding and key exposure freeness. Using this new scheme as kernel, an efficient and secure chameleon-based optimistic fair exchange protocol is proposed. Unlike the vast majority of previously proposed protocols, above approach has no use for verifiably encrypted signature and does not use any zero knowledge proofs, which avoids most of the costly computations. The security of the newly devised protocol is also examined. It is showed that the proposed scheme is secure and efficient.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122488516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture 传输触发体系结构中最小循环开销的软件流水线
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.18
Lei Jiang, Yongxin Zhu, Yipeng Wei
{"title":"Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture","authors":"Lei Jiang, Yongxin Zhu, Yipeng Wei","doi":"10.1109/ICESS.2008.18","DOIUrl":"https://doi.org/10.1109/ICESS.2008.18","url":null,"abstract":"On transport triggered architectures (TTAs) featuring huge scheduling freedom, parallelism is exploited at not only operation level, but also data transportation level. Software pipelining, an aggressive compiler optimization scheme for exploiting instruction level parallelism across loop iterations, has been studied extensively. However, only few efforts were focused on software pipelining on TTAs. In these existing works, intuitive yet less efficient methods were used, namely either modulo scheduling algorithm with some heuristics or parallel language to implement software pipelining on TTA. We propose a new software pipelining method on TTAs in order to fully evaluate the scope of scheduling freedom of TTA and take advantage of it. In this paper, we formulate the problem of constructing a resource constrained rate-optimal software pipelining with minimal loop overhead on TTAs as an integer linear programming (ILP) problem. The formulated problem is solved with GNU Linear Programming Kit (GLPK). We apply our approach to major loops in Livermore loop benchmarks. Comparing with the previous schedulers implemented with modulo scheduling algorithm, our ILP approach creates schedules which bring significant performance enhancement to applications on TTA.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124768127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Virus Detection Framework based on SPMOS 基于SPMOS的病毒检测框架
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.93
Tianzhou Chen, Jijun Ma, N. Zhang, Qingsong Shi
{"title":"A Virus Detection Framework based on SPMOS","authors":"Tianzhou Chen, Jijun Ma, N. Zhang, Qingsong Shi","doi":"10.1109/ICESS.2008.93","DOIUrl":"https://doi.org/10.1109/ICESS.2008.93","url":null,"abstract":"Embedded systems have been used in many different areas in which sensitive information communication and storage are needed. This makes security a serious concern in embedded system design, especially in operating system design. At the same time computer virus has been mutating and developing as fast as the upgrading speed of embedded operating system. Even it is possible for some intelligent virus to destroy the anti-virus software process in the memory. The system-on-a-chip technology provides Scratch-Pad Memory(SPM) which is physically isolated with main memory and more efficient than other kind of memories. We construct a demilitarized zone(DMZ) on SPM and design a small OS named SPMOS in the DMZ. A watchdog is contained in GPOS to monitor the events occurred. If an abnormal event is detected, GPOS will trap itself to SPMOS which will invoke anti-virus program. It is a big challenge to switch the two OSes without any virtual layer support. The way to protect SPM showed that the anti-virus detection platform based on SPMOS is secure. Then the experiment results show that the platform is efficient while switching between OSes.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123256276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Distributed Multisensor Estimation Fusion with Out-of-Sequence Measurements 无序测量的分布式多传感器估计融合
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.34
Donghua Wang, Yunmin Zhu, Xiaojing Shen
{"title":"Distributed Multisensor Estimation Fusion with Out-of-Sequence Measurements","authors":"Donghua Wang, Yunmin Zhu, Xiaojing Shen","doi":"10.1109/ICESS.2008.34","DOIUrl":"https://doi.org/10.1109/ICESS.2008.34","url":null,"abstract":"In the multiple sensor/sub-processor system, distributed estimation fusion based on the two level optimization strategy (optimal sensor estimations and optimal processor center fusion) are used widely. Optimal distributed estimation fusion with out-of-sequence measurements (OOSM) at local sensors is presented in this paper, its performance is equivalent to that of the corresponding Kalman filtering using all sensor observations (which is called the centralized Kalman filtering fusion).","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125546752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exploration of Low-Cost Configurable S-Box Designs for AES Applications 面向AES应用的低成本可配置S-Box设计探索
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.82
Jun-Hong Chen, Sue-Jing Huang, Wen-Ching Lin, Y. Lu, Ming-Der Shieh
{"title":"Exploration of Low-Cost Configurable S-Box Designs for AES Applications","authors":"Jun-Hong Chen, Sue-Jing Huang, Wen-Ching Lin, Y. Lu, Ming-Der Shieh","doi":"10.1109/ICESS.2008.82","DOIUrl":"https://doi.org/10.1109/ICESS.2008.82","url":null,"abstract":"Realizing AES in hardware faces increasingly more stringent demands for low cost as well as resisting power attacks. For security consideration, countermeasure power analysis approaches to mask sensitive data are needed. The algebraic masking method to protect AES against power attacks is based on various representations of underlying finite fields. However, implementing the transfer matrices between those fields requires a lot of memory spaces. In this paper, we propose a general method for sharing common subexpressions derived from the algebraic finite fields. Furthermore, we present a randomly configurable architecture for protecting SubByte transformation. Analytical results show that the proposed subexpression sharing method can significantly reduce up to 68.75% of memory requirement compared with individual implementations.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116600670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Novel Fast Intra Prediction Algorithm Applied in H.264/AVC H.264/AVC中一种新的快速帧内预测算法
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.16
Huixiao Feng, Yunhui Shi, Baocai Yin
{"title":"A Novel Fast Intra Prediction Algorithm Applied in H.264/AVC","authors":"Huixiao Feng, Yunhui Shi, Baocai Yin","doi":"10.1109/ICESS.2008.16","DOIUrl":"https://doi.org/10.1109/ICESS.2008.16","url":null,"abstract":"In H.264/AVC, a novel criterion named the rate distortion optimization (RDO) is employed to select the optimal coding modes for each macroblock (MB) within the intra prediction coding pictures, which can achieve a high compression ratio while leading to a great increase in the complexity and computational load unfortunately. In this paper, a DCT-based energy function is proposed, which is used to estimate the textural complexity of residual blocks of intra prediction. Then not more than 4 modes instead of 9 intra prediction modes for 4times4 block can be chosen to perform RDO according to the textural complexity of residual block. Consequently, the complexity decreases significantly. Experiments show that the proposed algorithm can save about 48% of the computation time stably while maintaining the PSNR-Bitrate performance of H.264/AVC.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134474649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance Improvement using Application-Specific Instructions under Hardware Constraints 在硬件约束下使用特定于应用程序的指令进行性能改进
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.30
Chijie Lin, Jiying Wu, Jerung Shiu, Chiuyun Hung, De-Sheng Chen, Yiwen Wang
{"title":"Performance Improvement using Application-Specific Instructions under Hardware Constraints","authors":"Chijie Lin, Jiying Wu, Jerung Shiu, Chiuyun Hung, De-Sheng Chen, Yiwen Wang","doi":"10.1109/ICESS.2008.30","DOIUrl":"https://doi.org/10.1109/ICESS.2008.30","url":null,"abstract":"An application-specific instruction-set processor (ASIP) is a technique that exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The generation and selection of Application-Specific Instructions (ASIs) dramatically affect the quality of an ASIP with design constraints such as number of register file I/Os and hardware cost. In this paper, a design flow is developed to automatically combine the disjoint operations as an ASI to enrich the selection varieties. The operation cover-ratio and the ASI latency model are used to select profitable ASIs so that the performance can be improved. The experimental results show the maximal 1.64x speed up can be obtained under hardware cost less than 8000 LEs in Altera FPGA.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133670618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Degree Priority Routing Algorithm for Irregular Mesh Topology NoCs 不规则网格拓扑noc的度优先路由算法
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.38
Ling Wang, Hui Song, Dongxin Wen, Yingtao Jiang
{"title":"A Degree Priority Routing Algorithm for Irregular Mesh Topology NoCs","authors":"Ling Wang, Hui Song, Dongxin Wen, Yingtao Jiang","doi":"10.1109/ICESS.2008.38","DOIUrl":"https://doi.org/10.1109/ICESS.2008.38","url":null,"abstract":"In this paper, a degree priority routing algorithm is proposed to minimize the hardware cost for nonregular mesh network-on-chip. In the algorithm, the routing path is dynamically selected with respective to the communication status of the next hop node. The next hop node concluded by the degree priority routing different with them obtained by routing algorithm are inserted in the routing table. And, the items in the routing table that have the same contents are combined to further minimize the area and power. Experimental results show that the proposed algorithm has better performance than other three routing algorithms.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133605003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An On-Line Hard Real-Time Communication Scheduler for Ultra-dependable System 一种用于超可靠系统的在线硬实时通信调度程序
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.48
Hui Chen, Zhidong Qin, X. Ju
{"title":"An On-Line Hard Real-Time Communication Scheduler for Ultra-dependable System","authors":"Hui Chen, Zhidong Qin, X. Ju","doi":"10.1109/ICESS.2008.48","DOIUrl":"https://doi.org/10.1109/ICESS.2008.48","url":null,"abstract":"It is important for ultra-dependable system to guarantee real-time performance. In this paper, an on-line hard real-time scheduling technique called HRTCS is presented, which is applicable for scheduling packets (messages) over a link. The scheduling technique can rapidly judge the schedulability and then automatically generate a bus table to schedule periodic and aperiodic packets. Using HRTCS not only guarantees the hard real time performance but also avoids the blockage and interruption of the packet transmission. Test results show that HRTCS can reduce the scheduling overhead and get higher bandwidth utilization than traditional scheduling algorithms. In addition, the FOLS policy of HRTCS provides a method to handle communication traffic variation rapidly during application system running. Therefore, HRTCS perfectly meets the demand of hard real-time communication on the ultra-dependable system.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132492325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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