2008 International Conference on Embedded Software and Systems最新文献_第3页

Formal Schedulability Analysis and Simulation for AADL AADL的形式化可调度性分析与仿真

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.63

Shenglin Gui, Lei Luo, Yun Li, Lijie Wang

{"title":"Formal Schedulability Analysis and Simulation for AADL","authors":"Shenglin Gui, Lei Luo, Yun Li, Lijie Wang","doi":"10.1109/ICESS.2008.63","DOIUrl":"https://doi.org/10.1109/ICESS.2008.63","url":null,"abstract":"With rapid developments in science and technology, we now see the ubiquitous use of different types of safety-critical systems in our daily lives such as in avionics, consumer electronics, and medical systems. In such systems, unintentional design faults might result in injury or even death to human beings. To make sure that safety-critical systems are really safe, only using the traditional methods is not enough. Model-Driven Architecture (MDA) method is becoming the mainstream as the instrument of the people. Architecture Analysis and Design Language (AADL) is a modeling language standard brought forward by the Society of Automotive Engineers, Avionics Systems Division, et al, is becoming a research topic for many organizations and institutes. It is a kind of MDA method also. For safety-critical systems, we must verify all the important properties whatever the method we use. Among the properties, the schedulability problem is a very important problem in the real-time software. But, how to solve the schedulability problem in a practical AADL project is a new obstacle to us. In this paper, we use the linear hybrid automata to abstract the semantics of the software components explicitly, then try to use TIMES tool developed by Uppsala Univ and Furness tool developed by Fremont Associates, LLC to simulate the semantics of linear hybrid automata and the scheduling execution trace of AADL software components respectively. Finally, we compare the two methods and make a conclusion.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114244334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Byzantine Fault Tolerance for Electric Power Grid Monitoring and Control 电网监测与控制的拜占庭容错

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.13

Wenbing Zhao, F. E. Villaseca

{"title":"Byzantine Fault Tolerance for Electric Power Grid Monitoring and Control","authors":"Wenbing Zhao, F. E. Villaseca","doi":"10.1109/ICESS.2008.13","DOIUrl":"https://doi.org/10.1109/ICESS.2008.13","url":null,"abstract":"The stability of the electric power grid is crucial to every nation's security and well-being. As revealed by a number of large-scale blackout incidents in North America, the data communication infrastructure for power grid is in urgent need of transformation to modern technology. It has been shown by extensive research work that such blackout could have been avoided if there were more prompt information sharing and coordination among the power grid monitoring and control systems. In this paper, we point out the need for Byzantine fault tolerance and investigate the feasibility of applying Byzantine fault tolerance technology to ensure high degree of reliability and security of power grid monitoring and control. Our empirical study demonstrated that Byzantine fault tolerant monitoring and control can easily sustain the 60 Hz sampling rate needed for supervisory control and data acquisition (SCADA) operations with sub-millisecond response time under the local-area network environment. Byzantine fault tolerant monitoring and control is also feasible under the wide-area network environment for power grid applications that demand sub-second reaction time.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122873107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A New Placement Approach to Minimizing FPGA Reconfiguration Data 最小化FPGA重构数据的一种新的放置方法

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.20

Weinan Chen, Y. Wang, Xiao-Wei Wang, Chenglian Peng

引用次数: 8

Power Management for Real-Time Embedded Systems on Block-Partitioned Multicore Platforms 块分割多核平台上实时嵌入式系统的电源管理

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.43

Xuan Qi, Dakai Zhu

引用次数: 19

Design a High-Performance Just-In-Time Compiler for a J2ME JVM on XScale 为XScale上的J2ME JVM设计一个高性能的即时编译器

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.55

Xiaohua Shi, Maozhong Jin, B. Cheng, Peng Guo

引用次数: 3

The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing 分组密码处理中可重构处理器体系结构的研究与实现

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.24

Z. Dai, Wei Li, Xiaohui Yang, Tao Chen, Qiao Ren

{"title":"The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing","authors":"Z. Dai, Wei Li, Xiaohui Yang, Tao Chen, Qiao Ren","doi":"10.1109/ICESS.2008.24","DOIUrl":"https://doi.org/10.1109/ICESS.2008.24","url":null,"abstract":"In the block ciphers, though the operation is quite complex, there are a lot of similar characteristics including arithmetic unit, operation width, parallel data and ordinal implement. It is very suitable for designing ASIP (application specific instruction set processor) targeted at block ciphers. In this thesis, a reconfigurable processor architecture is proposed, At the mean time, in order to improve instruction level parallelism. This thesis put forward the instruction bundle structure based on VLIW architecture, which supports word and sub-word parallel processing. As to the design of cipher arithmetic units, we adopt a specific design which is reconfigurable, so as to make the architecture have instruction level reconfigurable function. Besides, In order to solve the bottleneck of storage and access, this thesis adopt clustered technology to design two separated register files to storage data and subkey. Furthermore, this scheme reduces energy and clock cycles. A number of algorithms were implemented successfully on the processor. The prototype is realized using Alterapsilas FPGA. Synthesis, placement and routing of processor have accomplished under 0.18 mum CMOS technology through design complier tool. Compared with other ASIP targeted at block cipher, the results prove that processor can achieve relatively high performance in block cipher algorithms processing.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131039280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Reliability Demonstration Testing Method for Safety-Critical Embedded Applications Software 安全关键型嵌入式应用软件可靠性演示试验方法

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.76

Zhidong Qin, Hui Chen, Youqun Shi

引用次数: 4

Design of Fuzzy Feed-forward Decoupling System based on FPGA 基于FPGA的模糊前馈解耦系统设计

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.51

Yongqiang Guo, Kang-ling Fang, Hongjun Zhou

{"title":"Design of Fuzzy Feed-forward Decoupling System based on FPGA","authors":"Yongqiang Guo, Kang-ling Fang, Hongjun Zhou","doi":"10.1109/ICESS.2008.51","DOIUrl":"https://doi.org/10.1109/ICESS.2008.51","url":null,"abstract":"Coupling is a common phenomenon in process control system, which will decrease the performance of control systems. And what's worse, if the coupling is serious, the system can not work[1]. Therefore, it is significant to research decoupling in the fields of control theory and project practice. Nowadays, decoupling is always implemented by software. However, this method canpsilat satisfy the controlled plant for high speed because of bad real-time effect. Conversely, adopting the hardware decoupling could control the objects timely. There are many ways to realize decoupling by hardware, FPGA is an ideal method. FPGA is a kind of field programmable logical component, which adopts the EDA technology and uses hardware describing language as an expression of logic. It has many traits, such as shorter developing periods, higher speed, upgradeable online, and is suitable for teamwork. A kind of fuzzy feed-forward decoupling algorithm based on error[2] is applied in this paper. On one hand, with adopting fuzzy control, the algorithm does not rely on a mathematic model, and is able close to non-linearity. On the other hand, the speed of algorithm based on error is faster than the decoupling arithmetic based on output.Based on the analyses of a lot of coupling phenomenons, a kind of fuzzy feed-forward decoupling controller based on FPGA is designed in this paper. As a carrier with FPGA, the controller has smaller size, higher reliability, lower consumption and so on. With adopting the method of converting software idea to hardware circuit, the controller could improve the response speed. This paper chooses different plants as researching objects in the course of simulation and practice. According to the experimental results, the decoupling effect of the controller is obvious, which provides a feasible way for the development of the decoupling technology.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Research on the Self-localization of Wireless Sensor Networks 无线传感器网络的自定位研究

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.33

Xirong Bao, Shi Zhang, Dingyu Xue

引用次数: 6

The Optimal Kalman Type State Estimator with Multi-Step Correlated Process and Measurement Noises 具有多步相关过程和测量噪声的最优卡尔曼状态估计器

2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.54

An-qiu Fu, Yunmin Zhu, Enbin Song

引用次数: 17